Conference Papers
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Item Locating open-channels in octagon networks on chip-microprocessors(IEEE Computer Society help@computer.org, 2020) Bhowmik, B.; Biswas, S.; Deka, J.K.; Bhattacharya, B.B.Networks-on-chip (NoCs) provide the essential communication infrastructure for building today's on-chip multiprocessors. Albeit mesh is commonly used as the underlying interconnection architecture, other regular topologies such as octagons or spidergons, find recent applications to hybrid, small-world, and smart networks. Aggressive technology scaling, however, makes NoCs susceptible to manufacturing defects and causes failures in their operations. This paper presents a distributed, on-line built-in-self-test (BIST) mechanism that targets open faults on communication channels in an octagon NoC. We introduce a novel test scheduling scheme that exploits the knowledge of multithreading for reducing the overall test time with minimal degradation of performance. We evaluate the proposed test scheme for a 16-bit octagon NoC and report experimental results. © 2020 IEEE.Item Improving Reliability in Spidergon Network on Chip-Microprocessors(Institute of Electrical and Electronics Engineers Inc., 2020) Bhowmik, B.; Deka, J.K.; Biswas, S.Aggressive technology scaling continues to make networks-on-chip (NoCs) vulnerable to failures that relentlessly result in reliability concerns and unexpected system performance degradation. Therefore, there is an urgent demand for an effective test methodology that does not only improve the NoC's reliability but also prevent the system from being trapped into system-level failure modes. This paper presents a low-cost test scheme that addresses stuck-at faults in the communication channels of a Spidergon NoC. A built-in-self-test (BIST) method is presented to quickly detect the faults and reduce the affected application packets. The present test method is combined with a scheduling technique that together minimizes the test cost metrics, e.g., reduces 81.25% test time making the current test solution to become at least 5× faster. Furthermore, the solution shows less influence on system performance. © 2020 IEEE.Item Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels(Institute of Electrical and Electronics Engineers Inc., 2020) Bhowmik, B.; Biswas, S.; Deka, J.K.With the continuous growth in wire density, the reliability has become a dominant burden while channels of a modern NoC are exposed to various faults. A key requirement for the NoC is therefore to propose a mechanism that can account for a channel fault since it significantly impacts NoC performance. This paper presents a distributed test strategy that detects and diagnoses logic-level faults coexist in NoC channels and deeply analyze the severe impact of these faults on network performance. Fault coexistence in channels makes a fraction undetectable and is addressed here. Simulation results demonstrate the effectiveness of the proposed strategy. © 2020 IEEE.Item Reliability Monitoring in a Smart NoC Component(Institute of Electrical and Electronics Engineers Inc., 2020) Bhowmik, B.; Deka, J.K.; Biswas, S.SMART NoC topology components, such as octagon, spidergon are progressively becoming the primary design choice for implementing the communication backbone in a multi-core SoC platform for lowering a high number of inter-router hops required by long-range traffic. However, aggressive technology scaling has increased the number of transient/permanent faults raising the reliability concerns in a SMART NoC. This paper presents a reliability monitoring scheme for addressing channel-short faults in the basic octagon NoC. Along with the online detection and diagnosis of short faults, an effective scheduling scheme is proposed to provide a low-cost test solution that outperforms over a set of prior schemes. © 2020 IEEE.Item Selective Fault-Masking for Improving Yield and Performance of On-Chip Networks(Institute of Electrical and Electronics Engineers Inc., 2021) Bhowmik, B.; Deka, J.K.; Biswas, S.Nowadays, the reliability in network-on-chip (NoC) has become a crucial issue that leads to network performance degradation. Built-in-self-test (BIST) is one of the primary test schemes often used to achieve high reliability. The scheme allows a frequent test of and recovery from faults experienced on an NoC's fundamental component, e.g., communication channels. This paper presents a BIST approach that detects open and short faults in communication media to demonstrate the fault-masking phenomenon. The phenomenon as the self-repairing mode of the communication media improves the yield and performance of the NoCs. Rigorous simulations are made on an 8×8 mesh NoC with faulty and repaired channels. Results reveal that allowing faults in communication tracks degrades the network performance up to 30% while the self-repairing mode improves nearly 75%. © 2021 IEEE.Item Topology Exploration for Long-Distance Communication(Institute of Electrical and Electronics Engineers Inc., 2021) Gagan, N.; Bhowmik, B.With the increase in the network size, the conventional network-on-chip (NoC) imposes high latency due to the lack of shorter paths between far nodes resulting in performance degradation. This paper proposes an alternative approach that improves performance for long-distance communication in a mesh NoC. The proposed method explores a new topology named 'pseudo-3D mesh' in which a few new nodes are added in the upper layer of a 2D mesh NoC. Experimental results show that the proposed scheme provides acceptably high performance at the cost of little hardware over-head. © 2021 IEEE.Item Long-Distance Communication via Pseudo-3D Networks-on-Chip(Institute of Electrical and Electronics Engineers Inc., 2021) Gagan, N.; Bhowmik, B.Conventional mesh-based interconnection architecture is simple to implement and verify. However, with the increase in nodes and network size, the architecture imposes high latency due to the lack of shorter paths between far nodes. This paper finds an alternative approach that improves performance for long-distance communication in a mesh NoC. The proposed method offers a variant of the 2D mesh topology named 'pseudo-3D mesh' in which a few new nodes are added in the upper layer of a 2D mesh NoC. Rigorous simulation results show that the proposed scheme provides acceptably high performance at the cost of little hardware overhead. Further, the proposed method improves the global and local packet latency by 19% and 24%, respectively, compared to a conventional 2D 7 × 7 mesh NoC. Consequently, packet loss is improved by 50%, accelerating nearly 43% throughput gain and 47% energy consumption reduction. © 2021 IEEE.Item Reducing False Prediction on COVID-19 Detection Using Deep Learning(Institute of Electrical and Electronics Engineers Inc., 2021) Bhowmik, B.; Varna, S.A.; Kumar, A.; Kumar, R.This paper proposes a custom deep neural network-based scheme for coronavirus disease 2019 (COVID-19) detection. The proposed method takes X-ray images that use transfer learning techniques on pre-trained models. One objective of this work is to quickening the detection of the virus. Another goal is to reduce the number of falsely detected cases by a significant margin. The experimental setup demonstrates promising results on the selected dataset, which achieve up to 99.74%, 99.69%, 98.80% as classification, precision, and recall accuracy. © 2021 IEEE.Item Performance Evaluation in 2D NoCs Using ANN(Springer Science and Business Media Deutschland GmbH, 2022) Kale, P.; Hazarika, P.; Jain, S.; Bhowmik, B.A network-on-chip (NoC) performance is traditionally evaluated using a cycle-accurate simulator. However, when the NoC size increases, the time required for providing the simulation results rises significantly. Therefore, such an issue must be overcome with an alternate approach. This paper proposes an artificial neural network (ANN)-based framework to predict the performance parameters for NoCs. The proposed framework is learned with the training dataset supplied by the BookSim simulator. Rigorous experiments are performed to measure multiple performance metrics at varying experimental setups. The results show that network latency is in the range of 31.74–80.70 cycles. Further, the switch power consumption is in the range of 0.05–12.41 μ W. Above all, the proposed performance evaluation scheme achieves the speedup of 277–2304 × with an accuracy of up to 93%. © 2022, The Author(s), under exclusive license to Springer Nature Switzerland AG.Item TLM-NoC: Two Level Mesh Network-on-Chip for Performance Improvement(Institute of Electrical and Electronics Engineers Inc., 2022) Gagan, N.; Bhowmik, B.As the number of cores integrated into a system-on-chip (SoC) increases, the role played by this on-chip communication system becomes more and more critical due to communication bottleneck and scalability. The network-on-chip (NoC) design paradigm is today recognized as the most viable communication infrastructure over SoCs. However, the former architecture imposes latency concerns while the network size increases resulting in significant performance degradation. This paper finds an alternative solution for improving mesh NoCs, especially when long-distance communication takes place. The proposed solution suggests a variant of the 2D mesh topology named 'two-level mesh - network-on-chip (TLM-NoC)' in which a baseline mesh includes sparse mesh interconnection at the upper layer. The upper layer primarily establishes long-distance communications between nodes which in turn reduces latency and improves other metrics. Experimental results show adequate performance improvements by the TLM-NoC over traditional meshes. Evaluation of TLM-NoC shows latency improvement by 17.97%, resulting in 33.33% packet flit loss reduction and 26.80 % increased throughput. Further, the proposed architecture consumes 23.69% less energy for delivering traffic. © 2021 IEEE.