Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels

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Date

2020

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Institute of Electrical and Electronics Engineers Inc.

Abstract

With the continuous growth in wire density, the reliability has become a dominant burden while channels of a modern NoC are exposed to various faults. A key requirement for the NoC is therefore to propose a mechanism that can account for a channel fault since it significantly impacts NoC performance. This paper presents a distributed test strategy that detects and diagnoses logic-level faults coexist in NoC channels and deeply analyze the severe impact of these faults on network performance. Fault coexistence in channels makes a fraction undetectable and is addressed here. Simulation results demonstrate the effectiveness of the proposed strategy. © 2020 IEEE.

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Keywords

coexistent manufacturing channel-faults, nondiagnosable faults, on-chip communication interconnection architecture, on-line fault testing, performance analysis

Citation

Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics, 2020, Vol.2020-October, , p. 2339-2344

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