Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels
| dc.contributor.author | Bhowmik, B. | |
| dc.contributor.author | Biswas, S. | |
| dc.contributor.author | Deka, J.K. | |
| dc.date.accessioned | 2026-02-06T06:36:38Z | |
| dc.date.issued | 2020 | |
| dc.description.abstract | With the continuous growth in wire density, the reliability has become a dominant burden while channels of a modern NoC are exposed to various faults. A key requirement for the NoC is therefore to propose a mechanism that can account for a channel fault since it significantly impacts NoC performance. This paper presents a distributed test strategy that detects and diagnoses logic-level faults coexist in NoC channels and deeply analyze the severe impact of these faults on network performance. Fault coexistence in channels makes a fraction undetectable and is addressed here. Simulation results demonstrate the effectiveness of the proposed strategy. © 2020 IEEE. | |
| dc.identifier.citation | Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics, 2020, Vol.2020-October, , p. 2339-2344 | |
| dc.identifier.issn | 1062922X | |
| dc.identifier.uri | https://doi.org/10.1109/SMC42975.2020.9283106 | |
| dc.identifier.uri | https://idr.nitk.ac.in/handle/123456789/30580 | |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | |
| dc.subject | coexistent manufacturing channel-faults | |
| dc.subject | nondiagnosable faults | |
| dc.subject | on-chip communication interconnection architecture | |
| dc.subject | on-line fault testing | |
| dc.subject | performance analysis | |
| dc.title | Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels |
