Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels

dc.contributor.authorBhowmik, B.
dc.contributor.authorBiswas, S.
dc.contributor.authorDeka, J.K.
dc.date.accessioned2026-02-06T06:36:38Z
dc.date.issued2020
dc.description.abstractWith the continuous growth in wire density, the reliability has become a dominant burden while channels of a modern NoC are exposed to various faults. A key requirement for the NoC is therefore to propose a mechanism that can account for a channel fault since it significantly impacts NoC performance. This paper presents a distributed test strategy that detects and diagnoses logic-level faults coexist in NoC channels and deeply analyze the severe impact of these faults on network performance. Fault coexistence in channels makes a fraction undetectable and is addressed here. Simulation results demonstrate the effectiveness of the proposed strategy. © 2020 IEEE.
dc.identifier.citationConference Proceedings - IEEE International Conference on Systems, Man and Cybernetics, 2020, Vol.2020-October, , p. 2339-2344
dc.identifier.issn1062922X
dc.identifier.urihttps://doi.org/10.1109/SMC42975.2020.9283106
dc.identifier.urihttps://idr.nitk.ac.in/handle/123456789/30580
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.subjectcoexistent manufacturing channel-faults
dc.subjectnondiagnosable faults
dc.subjecton-chip communication interconnection architecture
dc.subjecton-line fault testing
dc.subjectperformance analysis
dc.titleTest Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels

Files