Skip navigation
Home
Browse
Communities
& Collections
Browse Items by:
Issue Date
Author
Supervisor
Title
Subject
Help
Sign on to:
My DSpace
Receive email
updates
Edit Profile
IR@NITK
Search
Search:
All of DSpace
1. Faculty Publications
2. Conference Papers
for
Current filters:
Title
Author
Subject
Date Issued
Has File(s)
???jsp.search.filter.original_bundle_filenames???
???jsp.search.filter.original_bundle_descriptions???
Equals
Contains
ID
Not Equals
Not Contains
Not ID
Title
Author
Subject
Date Issued
Has File(s)
???jsp.search.filter.original_bundle_filenames???
???jsp.search.filter.original_bundle_descriptions???
Equals
Contains
ID
Not Equals
Not Contains
Not ID
Title
Author
Subject
Date Issued
Has File(s)
???jsp.search.filter.original_bundle_filenames???
???jsp.search.filter.original_bundle_descriptions???
Equals
Contains
ID
Not Equals
Not Contains
Not ID
Title
Author
Subject
Date Issued
Has File(s)
???jsp.search.filter.original_bundle_filenames???
???jsp.search.filter.original_bundle_descriptions???
Equals
Contains
ID
Not Equals
Not Contains
Not ID
Start a new search
Add filters:
Use filters to refine the search results.
Title
Author
Subject
Date Issued
Has File(s)
???jsp.search.filter.original_bundle_filenames???
???jsp.search.filter.original_bundle_descriptions???
Equals
Contains
ID
Not Equals
Not Contains
Not ID
Results 1-9 of 9 (Search time: 0.003 seconds).
previous
1
next
Item hits:
Issue Date
Title
Author(s)
Supervisor(s)
2018
Floorplan based performance evaluation of 3d variants of mesh and BFT networks-on-chip
Halavar, B.
;
Talawar, B.
-
2018
FPGA based NoC Simulation Acceleration Framework Supporting Adaptive Routing
Parane, K.
;
Prabhu, Prasad, B.M.
;
Talawar, B.
-
2018
Near Optimal Solution for Traveling Salesman Problem using GPU
Yelmewad, P.
;
Talawar, B.
-
2018
Accurate Power and Latency Analysis of a Through-Silicon Via(TSV)
Pasupulety, U.
;
Halavar, B.
;
Talawar, B.
-
2018
Thermal Aware Design for Through-Silicon Via (TSV) based 3D Network-on-Chip (NoC) Architectures
Pasupulety, U.
;
Halavar, B.
;
Talawar, B.
-
2018
Machine Learning Based Framework to Predict Performance Evaluation of On-Chip Networks
Kumar, A.
;
Talawar, B.
-
2018
Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA
Sangeetha, G.S.
;
Radhakrishnan, V.
;
Prasad, P.
;
Parane, K.
;
Talawar, B.
-
2018
YaNoC: Yet another network-on-chip simulation acceleration engine using FPGAS
Parane, K.
;
Talawar, B.
;
Prabhu, Prasad, B.M.
-
2018
Accurate Performance Analysis of 3D Mesh Network on Chip Architectures
Halavar, B.
;
Talawar, B.
-
Discover
Author
4
Halavar, B.
3
Parane, K.
2
Pasupulety, U.
2
Prabhu, Prasad, B.M.
1
Kumar, A.
1
Prasad, P.
1
Radhakrishnan, V.
1
Sangeetha, G.S.
1
Yelmewad, P.