Please use this identifier to cite or link to this item:
Title: Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA
Authors: Sangeetha, G.S.
Radhakrishnan, V.
Prasad, P.
Parane, K.
Talawar, B.
Issue Date: 2018
Citation: Proceedings of the 2018 8th International Symposium on Embedded Computing and System Design, ISED 2018, 2018, Vol., , pp.129-134
Abstract: Networking On Chips is now becoming an extremely important part of the present and future of electronic technology. It is extensively used in Multiprocessor System-on-Chips and in Chip Multiprocessors. Using an NoC, the backend wiring involved has drastically reduced in an SoC. Further, SoCs with NoC interconnect operates at a higher operating frequency, mainly because the hardware required for switching and routing are simplified. The NoC researchers have relied on simulators based on performance and power to study the different factors of NoC such as algorithm in place, the topology, the buffer management and location schemes, the flow control and routing among others. In this paper, we present a trace-driven NoC architecture that gives the user access to realistic details about the resource utilization of NoC architectures and their individual components. This includes exploration of various design decision parameters of NoC by modeling them on a FPGA. The paper also presents the performance of these architectures by conducting trace-driven simulations using benchmarks like PARSEC. Different topologies are considered for experimentation purposes with different routing algorithms. � 2018 IEEE.
Appears in Collections:2. Conference Papers

Files in This Item:
There are no files associated with this item.

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.