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Title: Thermal Aware Design for Through-Silicon Via (TSV) based 3D Network-on-Chip (NoC) Architectures
Authors: Pasupulety, U.
Halavar, B.
Talawar, B.
Issue Date: 2018
Citation: Proceedings of the 2018 8th International Symposium on Embedded Computing and System Design, ISED 2018, 2018, Vol., , pp.236-240
Abstract: Through-Silicon Vias(TSVs) are a type of on-chip interconnect used for communication between multiple layers of circuit elements in a 3D IC. Multiple TSVs form a vertical link connecting inter-layer elements in 3D Network-on-Chip(NoC) architectures. Microarchitectural parameters such as length, width, pitch, and operating frequency influence the total power consumed and heat dissipated by TSVs. Effective extraction of the heat between layers is a significant challenge in 3D NoCs. Modelling the power of the TSVs and the thermal profile of 3D NoCs accurately enable designers perform trade-off studies during the design phase. In this work, we evaluate the thermal behaviour of 2 layer 3D Mesh and CMesh NoC architectures. We extended HotSpot to provide support for the inclusion of a router-TSV circuit element as a part of the 3D NoC floorplan. For the 3D Mesh, the thermal behaviour was analyzed for the naive arrangement as well as a proposed thermally aware design of the router-TSV element. Additionally, the thermal effect of multiple cores sharing a single router-TSV in a CMesh architecture was investigated. Our experiments show that the average of the maximum temperatures of all the routers in the 4x8x2 thermal-aware 3D Mesh is lowered by 3% compared to the naive 3D Mesh design. Also, the average of the maximum temperatures of all the routers in a 3D CMesh is 7% more than the naive 3D Mesh and 9% more than the thermally aware 3D Mesh design. � 2018 IEEE.
Appears in Collections:2. Conference Papers

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