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Results 11-19 of 19 (Search time: 0.003 seconds).
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Issue Date
Title
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Supervisor(s)
2018
Thermal Aware Design for Through-Silicon Via (TSV) based 3D Network-on-Chip (NoC) Architectures
Pasupulety, U.
;
Halavar, B.
;
Talawar, B.
-
2018
Machine Learning Based Framework to Predict Performance Evaluation of On-Chip Networks
Kumar, A.
;
Talawar, B.
-
2018
Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA
Sangeetha, G.S.
;
Radhakrishnan, V.
;
Prasad, P.
;
Parane, K.
;
Talawar, B.
-
2015
On the Cache Behavior of SPLASH-2 Benchmarks on ARM and ALPHA Processors in Gem5 Full System Simulator
Vikas, B.
;
Talawar, B.
-
2019
Accurate Router Level Estimation of Network-on-Chip Architectures using Learning Algorithms
Kumar, A.
;
Talawar, B.
-
2018
YaNoC: Yet another network-on-chip simulation acceleration engine using FPGAS
Parane, K.
;
Talawar, B.
;
Prabhu, Prasad, B.M.
-
2018
Accurate Performance Analysis of 3D Mesh Network on Chip Architectures
Halavar, B.
;
Talawar, B.
-
2015
A Crossbar Interconnection Network in DNA
Talawar, B.
-
2016
Cache analysis and software optimizations for faster on-chip network simulations
Parane, K.
;
Prabhu, Prasad, B.M.
;
Talawar, B.
-
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Parane, K.
5
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4
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2
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2
Yelmewad, P.
1
Kamath, A.
1
Prabhu, P.B.M.
1
Prasad, P.
1
Radhakrishnan, V.
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Date issued
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2018
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2019
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2016
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false