Faculty Publications
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Item Simulation and Modelling of screen oxide thickness dependent implantation peak position in Silicon(Institute of Electrical and Electronics Engineers Inc., 2020) Hegde, G.R.; Nikhil, K.S.; Rao, R.The relation between peak boron concentration position from the silicon-silicon dioxide interface (xp) after implantation through screen oxide with oxide thickness of (tox) is investigated in this paper. It is observed that the xp decreases with increase in tox. The rate of reduction is observed to be significantly higher for thin oxides. An empirical relation is proposed to model the oxide thickness dependent peak position with appropriate model parameters. © 2020 IEEE.Item Improvement in Breakdown Voltage of Junctionless Power Transistor with Ga2O3 RESURF region(Institute of Electrical and Electronics Engineers Inc., 2023) Manukrishna, V.R.; Nikhil, K.S.From the recent reported studies, it is clear that Ga2O3 can offer higher breakdown voltage due to its higher bandgap. However, Ga2O3 based power devices are having challenges like low carrier concentration and less electron mobility. In this article, a Junctionless Enhancement mode Field Effect Transistor (FET) with Ga2O3 REduced SURface Field (RESURF) is proposed. The introduction of n-Type Ga2O3 RESURF region between gate and drain region improves the breakdown voltage. The asymmetric gate structure further enhances the breakdown voltage by delaying the attainment of critical electric field. The variation of on resistance (RON) for varying the length of RESURF region (Lr) is also investigated. Junctionless FET with Ga2O3 RESURF has shown large potential for high power integrated circuit applications. © 2023 IEEE.Item Impact of Gate Oxide Thickness Variation on the On-state Safe Operating Area and FoM of SOI-Junctionless FinFET considering the Self-heating Effects(Institute of Electrical and Electronics Engineers Inc., 2024) Vinaya, S.J.; Nikhil, K.S.A 3D Silicon On Insulator-Junctionless FinFET (SOI-JLFinFET) device structure has been simulated to explore the impact of gate oxide thickness (tox) variation on performance metrics such as breakdown voltage, maximum drain current, and the safe operating area (SOA). To analyze the SOA thoroughly, simulations are done for SOI-JLFinFET with oxide thicknesses ranging from 2 nm to 5 nm. The effect of tox on the peak temperature of SOI-JLFinFET is also studied. The distribution of the electric field vector in the channel region has been examined for both thin and thick gate oxides. The device's performance for amplification application has also been assessed by obtaining the transconductance (gm) at different drain voltages. Furthermore, the overall effect of gate oxide thickness (tox) variation on the on-state breakdown voltage (Vbr,ON) and maximum drain current(ID,max), which impact the device's power handling capability and Figure of Merit (FoM) have been studied. © 2024 IEEE.Item Analysis of the non-monotonic dependence of FOM of β-Ga2O3based Junctionless Field Effect Transistor on doping profile linearity in the drift region(Institute of Electrical and Electronics Engineers Inc., 2024) Manukrishna, V.R.; Nikhil, K.S.In this work, the impact of variation of drift doping profile on the breakdown voltage and ON state power figure of merit (PFOM) of Variable Drift Doped Lateral β -Ga2O3Field Effect Transistor (VDDL-Ga2O3FET) has been reported. The variable lateral doping(VLD) technique was developed with an aim of attaining the minimum surface electric field through a drift region that is non-uniformly doped. In this work five devices namely Device A, Device B, Device C, Device D and Device E are simulated using synopsys sentaurus TCAD after applying VLD technique. The doping under source edge,gate region and drain edge are kept constant in all five devices. The region from gate edge to drain edge is divided into 2,3,4,5 and 10 in Device A, Device B, Device C, Device D and Device E respectively and variable doping is applied such a way that the concentration gradient between adjacent regions reduces as the number of regions increases. The TCAD simulation shows that Device C has maximum secondary breakdown voltage of 1353V and Device E gives maximum PFOM of 0.119MW/cm. Further investigation performed on critical electric field and impact ionization are in alignment with the results. © 2024 IEEE.Item INVESTIGATION OF THE IMPACT OF BURIED OXIDE LAYER IN UID LAYER AND CHANNEL REGION ON THE BREAKDOWN VOLTAGE AND THE THRESHOLD VOLTAGE OF β-GALLIUM OXIDE BASED POWER FETS(American Society of Mechanical Engineers (ASME), 2025) Manukrishna, V.R.; Nikhil, K.S.A ß-Ga2O3-based field-effect transistor with a buried oxide (BOX) layer is proposed for high-voltage applications such as electric vehicles and power ICs. In the proposed structure, the BOX layer is strategically incorporated within the channel region rather than extending into the unintentionally doped (UID) ß-Ga2O3 region. This placement effectively modulates the distribution of the electric field, mitigating the crowding of the peaK electric field near the drain side, and significantly improving the breaKdown voltage. The BOX layer, composed of silicon dioxide (SiO2), introduces additional capacitance, enhancing the electrostatic control of the gate over the channel. However, TCAD simulations reveal that variations in the thicKness of the BOX layer have minimal impact on the threshold voltage (Vtâ„Ž), indicating that the dominant factors governing Vtâ„Ž remain primarily associated with doping concentration and gate worK function. An empirical expression for the breaKdown voltage and an analytical expression for the threshold voltage, which incorporates the thicKness of the BOX layer, are derived and validated using TCAD test vectors. The redistribution of the electric field reduces impact ionization, enhances carrier transport, and improves overall device reliability, maKing the BOX-integrated JLFET a promising candidate for next-generation high-power and high-voltage electronics. © © 2025 by ASME.Item Optimization of the Properties of Functionalized BC3 Monolayer for Superior Electrode of Solid-State Sodium-Ion Batteries(John Wiley and Sons Inc, 2025) Vudumula, K.; Yadav, A.K.; Maurya, G.K.; Singh, R.; Nikhil, K.S.; Pandey, S.K.Solid-state batteries offer superior safety, high energy density, and the ability to function effectively across a wide range of temperatures. Sodium-ion (Na-ion) solid-state batteries are a promising alternative to lithium-ion batteries due to sodium's abundance and low cost. A high-quality electrode is crucial for achieving high performance in Na-ion batteries. In this study, structural stability, electronic properties, and performance of functionalized hexagonal boron carbide (BC3) are investigated for ultrathin electrodes using density functional theory (DFT). The effective adsorption of Li, Na, K, and Mg atoms at the BC3 surface is also investigated. The BC3 monolayer has a ?0.8 eV indirect bandgap, which becomes metallic after Na adsorption, making it suitable for electrode applications. Additionally, the Na-adsorbed BC3 monolayer shows the lowest adsorption energy (?1.2 eV), which is the most stable lattice structure among others. The Na-adsorbed BC3 demonstrated a theoretical capacity of 1152 mAh g?1, which is comparable with the Li-adsorbed electrode. Moreover, the Na-adsorbed BC3 electrode shows a very small variation (0.18 V) for open circuit voltage (OCV), indicating this electrode is robust in terms of voltage stability. These findings show that the functionalized BC3 ultrathin electrode is very suitable for the electrode of Na-ion solid-state batteries. © 2025 Wiley-VCH GmbH.Item Investigation of Performance Improvement in Drain Extended Longitudinal FinFETs for Thermal-aware Sustainable Electronics Applications(Springer Science and Business Media B.V., 2025) Nanjunda, A.; Nikhil, K.S.This work presents a comprehensive investigation of GaN-based Junctionless Drain Extended Longitudinal FinFET (DELFinFET) using Sentaurus TCAD simulations, targeting thermally robust and energy efficient semiconductor devices as a means to reduce the environmental footprint of electronic devices. Introducing a longitudinal fin achieves superior lateral electric field modulation, improved carrier transport, and enhanced electric control. This helps in improving the key analog performance metrics such as sub-threshold slope, leakage current (Ioff), transconductance (gm), and the switching ratio (Ion/Ioff). The results obtained highlight the potential of DELFinFET for low-power applications. A comparative evaluation is performed between the designed device and other device configurations to verify the effectiveness of the design. © The Author(s), under exclusive licence to Springer Nature B.V. 2025.Item Modeling of ?-Ga2O3 based double gate drain extended junction less FET and its parameter extraction methodology(Institute of Physics, 2025) Manukrishna, V.R.; Nikhil, K.S.A static current model of ?—Gallium Oxide (?-Ga2O3) based double gate drain extended junction less field effect transistor (DG-DeJLFET) is proposed. The model consists of two voltage-controlled current sources connected in series. One of the current sources accounts for the operation of the junction less field effect transistor whereas, the other takes care of the drift region current. The model is formulated by considering the mobility degradation caused by moderately elevated electric fields. A parameter extraction methodology for this model is also proposed by considering the dominance of certain parameters in the specific regions of operation. In general, the parameter extraction technique is based on the variation in the device current behavior at moderate electric fields. The proposed parameter extraction methodology is validated by comparing the results with the data obtained from the TCAD simulation. © 2025 IOP Publishing Ltd. All rights, including for text and data mining, AI training, and similar technologies, are reserved.Item A 0.5–5 Gb/s Wide Range, 160 fJ/Pulse Fully Integrated 13th-Order CMOS IR-UWB Transmitter for Wireless Capsule Endoscopy Systems(John Wiley and Sons Ltd, 2025) Akuri, N.; Kumar, K.; Kumar, S.; Nikhil, K.S.; Song, H.This paper proposes a novel technique based fully integrated 13th-order derivative CMOS impulse-radio ultrawideband (IR-UWB) transmitter with wide range of adaptive data rates for wireless capsule endoscopy systems (WCE). The proposed IR-UWB transmitter involves BPSK modulator-integrated RF power amplifier (PA) approach for WCE in first time as per author's best knowledge. The CMOS BPSK modulator with resonator technique generates 13th-order Modulated Gaussian pulse without the pulse generator. It has a peak-to-peak value of 25 mV and PSD level of ?72.60 dBm/MHz, data rate variability from 500 Mbps to 5 Gbps. The BPSK modulator with resonator is designed by time constant analysis in first time. In addition, a proposed CMOS PA is designed using four stacked transistors, which achieves a high output power as well as high efficiency for entire frequency band of operation from 3 to 16 GHz and wide impedance matching. The PA achieved an excellent gain of 16.55 dB with gain ripple of 0.25 dB only. Moreover, the PA achieved the saturated output power of 18.2 to 19.3 dBm with OP1dB of 15.96 to 16.72 dBm across entire bandwidth. Without violating FCC guidelines, PA strengths both peak-to-peak values, and PSD level of BPSK modulated signal to 80 mV and ?46.42 dBm/MHz. An IR-UWB transmitter has been implemented and fabricated using 65-nm CMOS Process, which consumes of only 160 fJ/pulse for generating Gaussian pulses order ranging from third-order to more than 13th-order at various data rates. © 2025 John Wiley & Sons Ltd.Item Investigation of the impact of gate oxide thickness variation of Junction-less FinFET using BSIM-CMG model for LIF neuron and STDP circuit application(Institute of Physics, 2025) Vinaya, S.J.; Rao, R.; Nikhil, K.S.In neuromorphic circuits, Leaky Integrate-and-Fire (LIF) neuron and Spike-Timing-Dependent Plasticity (STDP) circuits are very much essential. These circuits are significantly influenced by the characteristics of the transistors used in their design. In this work, the impact of gate oxide thickness variation on the performance of FinFET-based neuromorphic circuits using the (Berkeley Short-channel IGFET Model—Common Multi-Gate) BSIM-CMG model is investigated. TCAD simulations are carried out to analyze the electrical characteristics of FinFETs with varying oxide thicknesses. The circuit-level simulations are carried out using Cadence tool to evaluate their impact on synaptic weight updates in STDP and LIF neuron operation and circuits. The results show that reducing the gate oxide thickness from 5 nm to 2 nm enhances the capacitor voltage response, thereby improving charge storage and synaptic weight modulation. It has been shown that there is a consistent increase in capacitor voltage as oxide thickness decreases, which directly impacts the learning efficiency of STDP circuits. Varying oxide thickness will also impact on firing frequency of LIF neuron circuit.These results signifies performances of STDP and LIF neuron circuits for neuromorphic applications. © 2025 IOP Publishing Ltd. All rights, including for text and data mining, AI training, and similar technologies, are reserved.