Impact of Gate Oxide Thickness Variation on the On-state Safe Operating Area and FoM of SOI-Junctionless FinFET considering the Self-heating Effects
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Date
2024
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Publisher
Institute of Electrical and Electronics Engineers Inc.
Abstract
A 3D Silicon On Insulator-Junctionless FinFET (SOI-JLFinFET) device structure has been simulated to explore the impact of gate oxide thickness (t<inf>ox</inf>) variation on performance metrics such as breakdown voltage, maximum drain current, and the safe operating area (SOA). To analyze the SOA thoroughly, simulations are done for SOI-JLFinFET with oxide thicknesses ranging from 2 nm to 5 nm. The effect of t<inf>ox</inf> on the peak temperature of SOI-JLFinFET is also studied. The distribution of the electric field vector in the channel region has been examined for both thin and thick gate oxides. The device's performance for amplification application has also been assessed by obtaining the transconductance (g<inf>m</inf>) at different drain voltages. Furthermore, the overall effect of gate oxide thickness (t<inf>ox</inf>) variation on the on-state breakdown voltage (V<inf>br,ON</inf>) and maximum drain current(I<inf>D,max</inf>), which impact the device's power handling capability and Figure of Merit (FoM) have been studied. © 2024 IEEE.
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Keywords
Figure of Merit (FoM), Gate oxide thickness (tox), Maximum drain current (ID,max), On-state breakdown voltage (Vbr,ON), Safe operating area (SOA), SOI-Junctionless FinFET, Transconductance (gm)
Citation
ICACC - International Conference on Advances in Computing and Communications, 2024, Vol., 2024, p. -