Conference Papers

Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/28506

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    FARED: Fast adapting RED gateways for TCP/IP networks
    (2012) Tahiliani, M.P.; Shet, K.C.; Basavaraju, T.G.
    Random Early Detection (RED) is a widely deployed active queue management mechanism to improve the performance of the network in terms of throughput and packet drop rate. The effectiveness of RED, however, highly depends on appropriate setting of its parameters. In this paper, we propose a Fast Adapting Random Early Detection (FARED) algorithm which efficiently varies the maximum drop probability to improve the overall performance of the network. Based on extensive simulations, we show that FARED algorithm reduces the packet drop rate and achieves better throughput than Adaptive RED (ARED) and Refined Adaptive RED (Re-ARED). Moreover, FARED algorithm does not introduce new parameters to improve the performance and hence can be deployed without any additional complexity. © 2012 Springer-Verlag.
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    Design of Asynchronous Circular FIFO Buffer for Asynchronous Network on Chips
    (Institute of Electrical and Electronics Engineers Inc., 2022) Chaturvedi, S.; Saranya, M.N.; Rao, R.
    Network on Chip is employed for on-chip communication in multicore System-on-Chips for its advantages over bus-based architectures, more so with reducing feature size. The NoC implementation can be synchronous, asynchronous or Globally Asynchronous Locally Synchronous (GALS). However, synchronous design performance is limited by the global clock rate and depends on the slowest critical path, making it indispensable to optimize all portions of the design. Asynchronous design avoids clock skew and clock distribution issues on the chip and allows flexibility in the optimization of the rarely used portions of the system. Along with the benefit of reduced power consumption, they perform better in terms of delays, yielding average-case performance, as opposed to the worst-case performance yielded by the synchronous counterpart. One of the integral parts of NoC routers is buffers. In this paper, an asynchronous four-stage FIFO buffer based on domino logic and a synchronous four-stage FIFO buffer for comparison have been simulated using LTSpice on the TSMC 180nm technology. Results show that the proposed asynchronous design consumes 50% lesser power than the synchronous design, while maintaining a comparable performance in terms of latency and throughput. © 2022 IEEE.
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    Performance Evaluation of Wireless Health and Remote Monitoring Network Throughput Under Varying Conditions Using NetSim
    (Institute of Electrical and Electronics Engineers Inc., 2024) Pabitha, B.; Vani, V.; Sanshi, S.
    The Wireless Body Area Network (WBAN), organized in/out of the human body region to form Wireless enabled Health and Remote monitoring Network (WHRN), is trending on the medical platform for efficient diagnosis by the physician without the patient's physical visit. This network is framed with different biological sensors in the regional area of the human body to sense unlike biological signals promptly. Wearable WHRN, like smart watches and mobile phones, can notify people about stress, heart rate, and other physiological nods. The technology developed enhances the treatment for the patient, but the security of the information transmitted over different mediums is vulnerable. WHRN is simulated using the NetSim standard tool. Network performance metrics and their plots are analyzed using various encryption standards to provide data transmission and diagnosis security. Security is the primary concern for physiological data sensed and transmitted over different mediums. © 2024 IEEE.
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    Resource Allocation in Multi-Access Edge Computing using Teaching-Learning Based Optimization: A Multi-Objective Approach
    (Institute of Electrical and Electronics Engineers Inc., 2024) Al-Attabi, K.; Kumar, S.; Naik, A.V.; Bhagavanthu, M.; Reddy, R.A.
    Efficient resource allocation in Multi-access Edge Computing (MEC) plays a pivotal role in achieving high throughput, low latency, energy efficiency, and user fairness. Traditional optimization approaches often address these goals separately, leading to suboptimal solutions in dynamic environments with multifaceted user demands. This research proposes a multi-objective framework for resource allocation in MEC by leveraging the Teaching-Learning Based Optimization (TLBO) algorithm. The TLBO algorithm, inspired by the classroom learning process, iteratively improves a population of candidate solutions by sharing knowledge among learners and guidance from a 'teacher.' The research formulate the resource allocation problem as a multi-objective optimization problem and demonstrate how TLBO can effectively discover Pareto-optimal solutions that represent trade-offs between conflicting objectives. Experimental results on simulated MEC scenarios demonstrate the superiority of with throughput of 150 mbps the proposed approach compared to baseline strategies such as greedy of 135 mbps and weighted round robin of 142 mbps. © 2024 IEEE.
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    High Speed Data Compression Using FPGA
    (Institute of Electrical and Electronics Engineers Inc., 2025) Dileep Kumar, M.J.; de Castro, G.A.; Anusha, R.; P, P.; Srinivas, B.
    Efficient data compression is critical in modern digital systems to optimize storage and transmission bandwidth, especially in real-time applications. FieldProgrammable Gate Arrays (FPGAs) provide high-speed, hardware-accelerated solutions for data compression, offering parallel processing capabilities and reduced latency. This paper explores FPGA-based implementations of Run-Length Encoding (RLE) and Delta Encoding, two widely used lossless compression techniques. Performance is analyzed in terms of resource utilization, compression efficiency, power consumption, and scalability using the Xilinx Spartan-6 FPGA. Our results demonstrate that Delta Encoding achieves higher clock frequencies and lower power consumption, making it suitable for incremental data applications. In contrast, RLE excels in compressing redundant data sequences but has higher implementation complexity and variable throughput. The comparative study highlights the tradeoffs between these two methods and provides insights into their suitability for FPGA-based data compression in resourceconstrained environments. © 2025 IEEE.