Design of Asynchronous Circular FIFO Buffer for Asynchronous Network on Chips

Abstract

Network on Chip is employed for on-chip communication in multicore System-on-Chips for its advantages over bus-based architectures, more so with reducing feature size. The NoC implementation can be synchronous, asynchronous or Globally Asynchronous Locally Synchronous (GALS). However, synchronous design performance is limited by the global clock rate and depends on the slowest critical path, making it indispensable to optimize all portions of the design. Asynchronous design avoids clock skew and clock distribution issues on the chip and allows flexibility in the optimization of the rarely used portions of the system. Along with the benefit of reduced power consumption, they perform better in terms of delays, yielding average-case performance, as opposed to the worst-case performance yielded by the synchronous counterpart. One of the integral parts of NoC routers is buffers. In this paper, an asynchronous four-stage FIFO buffer based on domino logic and a synchronous four-stage FIFO buffer for comparison have been simulated using LTSpice on the TSMC 180nm technology. Results show that the proposed asynchronous design consumes 50% lesser power than the synchronous design, while maintaining a comparable performance in terms of latency and throughput. © 2022 IEEE.