Conference Papers

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    An Image Transmission Technique using Low-Cost Li-Fi Testbed
    (Institute of Electrical and Electronics Engineers Inc., 2021) Salvi, S.; Geetha, V.; Maru, H.; Kumar, N.; Ahmed, R.
    Visible Light Communication (VLC) or Light Fidelity (Li-Fi) with Light Emitting Diodes (LEDs) as transmitter and light sensor as receiver will turn the present lightening system into a communication system. Li-Fi based data communication provides secure communication within the luminous coverage of the light source. Thus, it has several applications in places where Radio Frequency interference is not desirable. Similar to other wireless communication techniques even Li-Fi is used for transmission and reception of digital data. Li-Fi system can also be used to transfer images from one device to another. In this paper, a preliminary study is discussed by proposing and implementing an encoding and decoding scheme for transmission of the binary image using Li-Fi. The proposed system is evaluated based on the light intensity, distance, accuracy, size of the image, image resolution, and transmission time. © 2021 IEEE.
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    A Framework for SOT-MRAM Scaling Road-Map with Density and Application Evaluation
    (Institute of Electrical and Electronics Engineers Inc., 2024) Kallinatha, D.H.; Talawar, B.
    The increasing difference between CPU speeds and memory access times, known as the 'Memory Wall' problem, poses considerable challenges in modern computing. This study introduces a scaling factor framework to integrate Spin-Orbit-Torque Magnetic RAM(SOT-MRAM) into cache architectures as a potential replacement for Static Random Access Memory(SRAM). This research primarily targets applications in artificial intelligence (AI), natural language processing(NLP), and broad computing tasks. It presents a method to evaluate the effectiveness of scaling factor framework and density enhancement in cache memory through the proposed frame-work's extensive Design Space Exploration(DSE). This exploration includes a detailed comparative analysis of SRAM and SOT-MRAM under various scaling conditions within the L2 and Last-Level Cache(LLC) segments. The outcomes indicate that SOT-MRAM significantly improves energy efficiency and reduces latency, achieving a 60% decrease in power usage and a 75% enhancement in response times compared to conventional SRAM caches. These advancements suggest that SOT-MRAM could effectively mitigate the challenges the Memory Wall poses, enhancing overall computational performance. © 2024 IEEE.
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    High Speed Data Compression Using FPGA
    (Institute of Electrical and Electronics Engineers Inc., 2025) Dileep Kumar, M.J.; de Castro, G.A.; Anusha, R.; P, P.; Srinivas, B.
    Efficient data compression is critical in modern digital systems to optimize storage and transmission bandwidth, especially in real-time applications. FieldProgrammable Gate Arrays (FPGAs) provide high-speed, hardware-accelerated solutions for data compression, offering parallel processing capabilities and reduced latency. This paper explores FPGA-based implementations of Run-Length Encoding (RLE) and Delta Encoding, two widely used lossless compression techniques. Performance is analyzed in terms of resource utilization, compression efficiency, power consumption, and scalability using the Xilinx Spartan-6 FPGA. Our results demonstrate that Delta Encoding achieves higher clock frequencies and lower power consumption, making it suitable for incremental data applications. In contrast, RLE excels in compressing redundant data sequences but has higher implementation complexity and variable throughput. The comparative study highlights the tradeoffs between these two methods and provides insights into their suitability for FPGA-based data compression in resourceconstrained environments. © 2025 IEEE.