A Framework for SOT-MRAM Scaling Road-Map with Density and Application Evaluation

Abstract

The increasing difference between CPU speeds and memory access times, known as the 'Memory Wall' problem, poses considerable challenges in modern computing. This study introduces a scaling factor framework to integrate Spin-Orbit-Torque Magnetic RAM(SOT-MRAM) into cache architectures as a potential replacement for Static Random Access Memory(SRAM). This research primarily targets applications in artificial intelligence (AI), natural language processing(NLP), and broad computing tasks. It presents a method to evaluate the effectiveness of scaling factor framework and density enhancement in cache memory through the proposed frame-work's extensive Design Space Exploration(DSE). This exploration includes a detailed comparative analysis of SRAM and SOT-MRAM under various scaling conditions within the L2 and Last-Level Cache(LLC) segments. The outcomes indicate that SOT-MRAM significantly improves energy efficiency and reduces latency, achieving a 60% decrease in power usage and a 75% enhancement in response times compared to conventional SRAM caches. These advancements suggest that SOT-MRAM could effectively mitigate the challenges the Memory Wall poses, enhancing overall computational performance. © 2024 IEEE.