Browsing by Author "Kallinatha, H.D."

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A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment
(Institute of Electrical and Electronics Engineers Inc., 2024) Kallinatha, H.D.; Rai, S.; Talawar, B.
As the current primary memory technology is reaching its limits, it is essential to explore alternative memory technologies to accommodate modern applications and use cases. However, using new memory technology poses the challenge of deriving accurately estimated parameters for integrating new memory technology and doing reliable simulations. This study proposes a new approach incorporating Spin-Orbit-Torque-Magnetic-RAM (SOT-MRAM) into hybrid and full main memory architectures within a multi-core system, encompassing various memory configurations and capacities. The study addresses the challenge of evaluating SOT-MRAM-based memory systems when specific SOT-MRAM memory parameters are not publicly available. The research methodology includes micro-architectural (circuit-level) design space exploration and comprehensive full system simulations, which evaluate benchmark programs representing diverse application domains. The evaluation includes three memory structures with varying memory organizations and capacities. The results show that SOT-MRAM is a robust replacement for DRAM or hybrid memory, offering compelling advantages such as a remarkable 74.05% reduction in power consumption, a noteworthy 40.10% increase in bandwidth utilization, and a significant 72.85% reduction in Energy-Delay Product (EDP). The maximum latency penalties are also minimal, with a 3.71% increase for hybrid structures and a mere 0.07% for standalone SOT-MRAM memory structures. © 2013 IEEE.
Comparative analysis of non-volatile memory on-chip caches
(American Institute of Physics Inc., 2023) Kallinatha, H.D.; Talawar, B.
The SRAM on-chip caches occupy a significant chip area and consume substantial power in modern processors. This paper aims to study the emerging Non-Volatile Memory (NVM) systems suitability for memory hierarchy beyond CMOS. NVMs have ultra-low leakage, better scalability and consume less energy. The NVM technologies such as STT-MRAM, ReRAM and PCM suffer from write endurance and read disturbance problems. The new spintronics technology, such as spin orbit-torque (SOT) switching based magneto resistive (MRAM) memory, can overcome the issues in STT-MRAM. So, this paper aims to study the impact of small to sizable on-chip memory in full exploration mode of the simulator for estimation of the energy, area, leakage power and per access latency of memory technologies. We present a detailed comparative analysis of NVMs and SRAM at 45nm. The study concludes that the SOT-MRAM area is smaller for cache size above 64KB and faster than 32KB. In addition, this consumes less energy above 128KB and reduces leakage power above 16KB compared to SRAM. Significant benefits of SOT-MRAM are that it provides area efficiency of 57.29%, speedup of 3.27 times faster and 94.53% less leakage power than SRAM. Â© 2023 Author(s).
SOT-MRAM Based Main Memory: An Alternative to DRAM
(Institute of Electrical and Electronics Engineers Inc., 2022) Rai, S.; Kallinatha, H.D.; Talawar, B.
Data is generated enormously today and to process this we need large memories with high speed and optimized power consumption. Conventional DRAM based system which were used as memory in computing systems for several decades are facing challenges in scalability and power consumption. In this regard non-volatile memories with excellent scalability and minimal power consumption are studied extensively. This paper analyzes the impact of introducing SOT-MRAM a non-volatile main memory device as an alternative to DRAM. Experimental results show an average power reduction of 46.09% with an increase in performance up to 30% when DRAM is replaced with SOT-MRAM for embedded system workloads. Â© 2022 IEEE.
SOT-MRAM Devices inÂ Memory Hierarchy forÂ Next-Generation Computing Systems
(Springer Science and Business Media Deutschland GmbH, 2025) Kallinatha, H.D.; Talawar, B.
This work introduces a Multi-Factor Scaling (MFS) framework to utilize Spin-Orbit-Torque Magnetic RAM (SOT-MRAM) as a substitute for traditional SRAM caches, which face scalability and efficiency issues with CMOS technology down-scaling. With distinct read/write paths and superior endurance, SOT-MRAM is evaluated for artificial intelligence (AI), natural language processing (NLP), and general-purpose applications. The MFS framework assesses the impact of SOT-MRAM on-chip cache design through Design Space Exploration (DSE) and density replacement studies, comparing it against SRAM configurations. The research proposes and explores a Physically Split Cache (PSC) design with Virtual Reordering (VRO) to manage Write Variation (WVAR) dynamically, aiming to prolong cache lifetime and reliability. Furthermore, the potential of SOT-MRAM to replace DRAM in main memory is investigated despite the challenge of limited parameter availability with reliable simulations. Â© The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.
Spintronics Main Memory Alternative to DRAM with Reliable Simulations
(Institute of Electrical and Electronics Engineers Inc., 2023) Kallinatha, H.D.; Talawar, B.
This study introduces a new approach to integrate SOT-MRAM into hybrid and full main memory architectures in a multi-core system. The study overcomes the challenge of limited publicly available SOT-MRAM parameters for reliable simulation. In this work, we conducted micro-architectural design space exploration and full system simulations to highlight the potential of SOT-MRAM. The study shows that SOT-MRAM offers remarkable power reduction, bandwidth increase, and a reduction in Energy-Delay Product (EDP) with minimal latency impact. Even with scaled current and timing parameters, SOTMRAM outperforms DRAM. This approach has opened up new possibilities for energy-efficient memory systems that could significantly improve the performance of multi-core systems. Â© 2023 IEEE.