Comparative analysis of non-volatile memory on-chip caches

Abstract

The SRAM on-chip caches occupy a significant chip area and consume substantial power in modern processors. This paper aims to study the emerging Non-Volatile Memory (NVM) systems suitability for memory hierarchy beyond CMOS. NVMs have ultra-low leakage, better scalability and consume less energy. The NVM technologies such as STT-MRAM, ReRAM and PCM suffer from write endurance and read disturbance problems. The new spintronics technology, such as spin orbit-torque (SOT) switching based magneto resistive (MRAM) memory, can overcome the issues in STT-MRAM. So, this paper aims to study the impact of small to sizable on-chip memory in full exploration mode of the simulator for estimation of the energy, area, leakage power and per access latency of memory technologies. We present a detailed comparative analysis of NVMs and SRAM at 45nm. The study concludes that the SOT-MRAM area is smaller for cache size above 64KB and faster than 32KB. In addition, this consumes less energy above 128KB and reduces leakage power above 16KB compared to SRAM. Significant benefits of SOT-MRAM are that it provides area efficiency of 57.29%, speedup of 3.27 times faster and 94.53% less leakage power than SRAM. © 2023 Author(s).