A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment

No Thumbnail Available

Date

2024

Journal Title

Journal ISSN

Volume Title

Publisher

Institute of Electrical and Electronics Engineers Inc.

Abstract

As the current primary memory technology is reaching its limits, it is essential to explore alternative memory technologies to accommodate modern applications and use cases. However, using new memory technology poses the challenge of deriving accurately estimated parameters for integrating new memory technology and doing reliable simulations. This study proposes a new approach incorporating Spin-Orbit-Torque-Magnetic-RAM (SOT-MRAM) into hybrid and full main memory architectures within a multi-core system, encompassing various memory configurations and capacities. The study addresses the challenge of evaluating SOT-MRAM-based memory systems when specific SOT-MRAM memory parameters are not publicly available. The research methodology includes micro-architectural (circuit-level) design space exploration and comprehensive full system simulations, which evaluate benchmark programs representing diverse application domains. The evaluation includes three memory structures with varying memory organizations and capacities. The results show that SOT-MRAM is a robust replacement for DRAM or hybrid memory, offering compelling advantages such as a remarkable 74.05% reduction in power consumption, a noteworthy 40.10% increase in bandwidth utilization, and a significant 72.85% reduction in Energy-Delay Product (EDP). The maximum latency penalties are also minimal, with a 3.71% increase for hybrid structures and a mere 0.07% for standalone SOT-MRAM memory structures. © 2013 IEEE.

Description

Keywords

Application programs, Benchmarking, Magnetic recording, Memory architecture, MRAM devices, Nonvolatile storage, Phase change materials, Phase change memory, High performance systems, Hybrid power, Hybrid power system, Magnetic tunneling, Memory-management, Modeling, Non-volatile memory, Nonvolatile memory, Random access memory, Simulation, System, Timing, VLSI, Dynamic random access storage

Citation

IEEE Access, 2024, 12, , pp. 7224-7243

Collections

Endorsement

Review

Supplemented By

Referenced By