Faculty Publications
Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736
Publications by NITK Faculty
Browse
7 results
Search Results
Item A high efficiency on-chip reconfigurable Doherty power amplifier for LTE communication cells(John Wiley and Sons Inc. P.O.Box 18667 Newark NJ 07191-8667, 2018) Kumar, R.; Kanuajia, B.K.; Dwari, S.; Kumar, S.; Song, H.In this paper, a high efficiency on-chip reconfigurable Doherty power amplifier (DPA) with proposed topology is proposed for LTE or 4G communication cells. The proposed DPA consists of input driver topology, hybrid coupler, asymmetric amplifiers, and 1:1 balun filtered network. The proposed input driver circuit provides wide amplified signal operation within range of 2.3GHz to 6GHz with flat gain of 33 dB. The amplified signal is unsteadily divided into two paths toward the carrier and the power amplifier by 900 hybrid couplers and demonstrates 27.6 dB and 28.3 dB of gain along with 83.2% and 84.5% of power added efficiency at average output power of 40 dBm. The high efficiency and almost flatness in gain stability of proposed DPA providing better solution in order to overcome the interference and the broadband issues for LTE communication cells. The balun-filtered network is employed for combined the two outputs of carrier and peak amplifiers that provides more uniform desired band of operation in the frequency responses. The proposed DPA circuit are implemented and optimized by using advanced design RF simulator platform. The fabricated chip is made by using 0.13 ?m GaN HEMT on Si-Nitride monolithic microwave integrated circuit die process. The fabricated chip of DPA provides 85% of PAE with 28 dB gain which are made close agreement with simulation results. The size of chip is 2.8*1.2mm2 which occupies less die area as compared to existing DPAs. © 2018 Wiley Periodicals, Inc.Item A 8–12 GHz, 44.3 dBm RF output class FF?1 DPA using quad-mode coupled technique for new configurable front-end 5G transmitters(Springer, 2021) Kumar, R.; Dwari, S.; Kumar Kanaujia, B.K.; Kumar, S.; Song, H.This paper presents a high-efficiency Class FF - 1 DPA using the quad-mode coupled technique for new configurable front-end 5G transmitters. The proposed DPA consists of carrier PA, main PA, input–output matching network and hybrid power network (HPN). The HPN includes a quad-mode coupled technique which is four-section U-shaped transmission line. The HPN is used for even–odd mode impedance analysis to ensures the high-selectivity of output power and achieve a wideband response in the presence of harmonic control conditions. The optimum harmonic impedance is analyzed for the desired band to achieve high output power and efficiency. The DPA circuit is fabricated by using 0.25 µm GaN HEMT on silicon nitride monolithic microwave integrated circuit die process. At maximum output power level of 44.3 dBm, the delivered power-added efficiency (PAE) of 64.3–67.3% and drain efficiency (DE) of 71.7–73.7% at even–odd mode operation are achieved with a gain of 13.0–14.3 dB. For the output power level of 39.045 dBm corresponding to 9 dB output back-off (OBO), the drain efficiency lies between 55–62% with 73% fractional bandwidth. All the demonstrated transmission parameters are working in the band of 8–12 GHz. The size of the chip is 2.8 × 1.9 mm2 and it occupies less die area as compared to the existing DPAs. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.Item A wideband, 25/40dBm high I/O power GaN HEMT ultra-low noise amplifier using even-odd mode techniques(Elsevier Ltd, 2022) Gupta, M.P.; Gorre, P.; Kumar, S.; Nulu, V.This paper presents a performance analysis of the low noise amplifier (LNA) for the first time using even-odd mode matching techniques in Gallium Nitride (GaN) HEMT Technology for marine communication. The proposed GaN LNA circuit consists of broadband stage I, main amplifier, and inverted broadband stage II, which provides a high input/output power, and ultra-low noise over wide bandwidth ranging from 0.5 GHz to 2.7 GHz with fractional impedance bandwidth of 138%. Broadband Stage I and Inverted broadband stage II are employed to provide input/output impedance matching transformation. The proposed LNA circuit with the incorporation of input/output broadband stages relax a 50Ω matching constraints and achieved high input and output power with good stability. The GaN HEMT LNA is analyzed and simulated using the RF simulator (ADS tool). The proposed GaN HEMT LNA is fabricated on RT Duroid substrate using Microwave Integrated Circuit (MIC) technology. The proposed LNA achieves a measured gain of 16 dB, while the simulated one is 17 dB with good insertion loss. An ultra-low noise figure of 0.6 dB flat is achieved over a wide bandwidth. In addition, the high output power is achieved 40dBm while input power is 25dBm which could overcome weak signal strength received by RF receiver for marine communication. A stability factor greater than one is achieved over a broad band ranging from 0.5 GHz to 2.7 GHz. The fabricated GaN HEMT LNA circuit has consumed power of 120 mW under a supply of 28 V. The area of the fabricated RF GaN HEMT LNA is 32 × 26 mm2. © 2022 Elsevier LtdItem A 0.15 μm GaN HEMT device to circuit approach towards dual-band ultra-low noise amplifier using defected ground bias technique(Elsevier GmbH, 2023) Gupta, M.P.; Kumar, S.; Elizabeth Caroline, B.; Song, H.; Kumar, V.; Gorre, P.This work presents a GaN HEMT device to circuit approach towards low noise amplifier (LNA) using defective ground bias (DGB) technique. This is the first MMIC GaN HEMT LNA design to offer dual-band of operation in both L and S-bands to the author's best knowledge. The proposed 0.15-μm GaN HEMT device fabrication achieves a high output power of 20 W using slot radiation phenomenon. The proposed DGB technique consists of gate and drain biasing topologies which achieves a dual-band of operation using microwave approach. The DGB technique is incorporated into GaN HEMT LNA which achieves high input and output power with good stability. To achieve an optimal noise, high I/O power, and almost flat gain at both L and S-bands, the defective ground structure of bias topologies is modeled and optimized. An artificial ground defect is created to offer resonant properties for the DGS of a microstrip line, which utilizes frequency-selective properties to improve the performance of the LNA circuit by suppressing the harmonics and scaling the size. The dedicated LNA shows the benefits of compact size, extremely low noise figure of 0.74/1.6 dB, high output power of 44 dBm and nearly flat gain of 14/11 dB at 1.17/2.49 GHz with the unique methodologies suggested. The compact GaN HEMT LNA could overcome the weak signal strength received by RF receiver for smart rail transport system. © 2023 Elsevier GmbHItem A new design approach of Rat-Race coupler based compact GaN HEMT power amplifier towards flat high efficiency over broadband(Elsevier GmbH, 2024) Gupta, M.P.; Kumar, S.; Naik Jatoth, D.; Gorre, P.; Song, H.This paper presents a high efficiency Rat-Race Coupler based compact GaN HEMT power amplifier (PA) design over broadband for high power transmitter in wireless communication. The rat-race coupler integrated PA Compact design is proposed for the first time as per author best knowledge. The design methodology used a higher order two open stubs and a rat-race coupler (RRC) at input/output sections to control harmonics impedances. The RRC is used to enhance the i/o power, and efficiency over broadband, which provides a good insertion loss, and consumes the least power and non-crucial impedance bandwidth for the normalized frequency band of interest. As a proof of concept, a PA is fabricated using a monolithic microwave integrated circuit (MMIC) 0.15 µm gallium nitride high electron mobility transistor (GaN HEMT) process. The measured result shows that the designed PA achieves a flat power added efficiency (PAE) of 65 % − 74 %, output power (Pout) of 44.8 dBm − 46 dBm, and drain efficiency (DE) of 72 % − 85 %, over a record wide frequency of 1.8 GHz − 3.6 GHz, which is the highest one among all reported harmonic tuned PAs. © 2024 Elsevier GmbHItem Investigation of Performance Improvement in Drain Extended Longitudinal FinFETs for Thermal-aware Sustainable Electronics Applications(Springer Science and Business Media B.V., 2025) Nanjunda, A.; Nikhil, K.S.This work presents a comprehensive investigation of GaN-based Junctionless Drain Extended Longitudinal FinFET (DELFinFET) using Sentaurus TCAD simulations, targeting thermally robust and energy efficient semiconductor devices as a means to reduce the environmental footprint of electronic devices. Introducing a longitudinal fin achieves superior lateral electric field modulation, improved carrier transport, and enhanced electric control. This helps in improving the key analog performance metrics such as sub-threshold slope, leakage current (Ioff), transconductance (gm), and the switching ratio (Ion/Ioff). The results obtained highlight the potential of DELFinFET for low-power applications. A comparative evaluation is performed between the designed device and other device configurations to verify the effectiveness of the design. © The Author(s), under exclusive licence to Springer Nature B.V. 2025.Item Temperature dependence of linearity parameters of GaN-based junctionless drain extended FinFET(Elsevier Ltd, 2025) Ashwini, N.; Nikhil, K.S.In this work, temperature dependent linearity parameters of Galliun Nitride (GaN, a wide gap material) based Junctionless Drain Extended FinFETs (JLDEFinFETs) for a temperature ranging from 100K to 450K are investigated using 3D thermodynamic TCAD simulation. An analysis of the transfer characteristics, off-current, transconductance, and its derivatives are carried out at various temperatures. Additionally, the impact of various linearity parameters, such as VIP2, VIP3, IIP3, IMD3, and the 1-dB compression point on temperature is studied in detail. The device under consideration has a metal gate contact which offers opportunities to tune its performance parameters like on-current, off-current and threshold voltage. A comparative analysis of the designed device with various devices is also carried out to validate the device design. © 2025 Elsevier Ltd