Faculty Publications
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Item Investigation of Performance Improvement in Drain Extended Longitudinal FinFETs for Thermal-aware Sustainable Electronics Applications(Springer Science and Business Media B.V., 2025) Nanjunda, A.; Nikhil, K.S.This work presents a comprehensive investigation of GaN-based Junctionless Drain Extended Longitudinal FinFET (DELFinFET) using Sentaurus TCAD simulations, targeting thermally robust and energy efficient semiconductor devices as a means to reduce the environmental footprint of electronic devices. Introducing a longitudinal fin achieves superior lateral electric field modulation, improved carrier transport, and enhanced electric control. This helps in improving the key analog performance metrics such as sub-threshold slope, leakage current (Ioff), transconductance (gm), and the switching ratio (Ion/Ioff). The results obtained highlight the potential of DELFinFET for low-power applications. A comparative evaluation is performed between the designed device and other device configurations to verify the effectiveness of the design. © The Author(s), under exclusive licence to Springer Nature B.V. 2025.Item Investigation of the impact of gate oxide thickness variation of Junction-less FinFET using BSIM-CMG model for LIF neuron and STDP circuit application(Institute of Physics, 2025) Vinaya, S.J.; Rao, R.; Nikhil, K.S.In neuromorphic circuits, Leaky Integrate-and-Fire (LIF) neuron and Spike-Timing-Dependent Plasticity (STDP) circuits are very much essential. These circuits are significantly influenced by the characteristics of the transistors used in their design. In this work, the impact of gate oxide thickness variation on the performance of FinFET-based neuromorphic circuits using the (Berkeley Short-channel IGFET Model—Common Multi-Gate) BSIM-CMG model is investigated. TCAD simulations are carried out to analyze the electrical characteristics of FinFETs with varying oxide thicknesses. The circuit-level simulations are carried out using Cadence tool to evaluate their impact on synaptic weight updates in STDP and LIF neuron operation and circuits. The results show that reducing the gate oxide thickness from 5 nm to 2 nm enhances the capacitor voltage response, thereby improving charge storage and synaptic weight modulation. It has been shown that there is a consistent increase in capacitor voltage as oxide thickness decreases, which directly impacts the learning efficiency of STDP circuits. Varying oxide thickness will also impact on firing frequency of LIF neuron circuit.These results signifies performances of STDP and LIF neuron circuits for neuromorphic applications. © 2025 IOP Publishing Ltd. All rights, including for text and data mining, AI training, and similar technologies, are reserved.Item Temperature dependence of linearity parameters of GaN-based junctionless drain extended FinFET(Elsevier Ltd, 2025) Ashwini, N.; Nikhil, K.S.In this work, temperature dependent linearity parameters of Galliun Nitride (GaN, a wide gap material) based Junctionless Drain Extended FinFETs (JLDEFinFETs) for a temperature ranging from 100K to 450K are investigated using 3D thermodynamic TCAD simulation. An analysis of the transfer characteristics, off-current, transconductance, and its derivatives are carried out at various temperatures. Additionally, the impact of various linearity parameters, such as VIP2, VIP3, IIP3, IMD3, and the 1-dB compression point on temperature is studied in detail. The device under consideration has a metal gate contact which offers opportunities to tune its performance parameters like on-current, off-current and threshold voltage. A comparative analysis of the designed device with various devices is also carried out to validate the device design. © 2025 Elsevier Ltd