Faculty Publications
Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736
Publications by NITK Faculty
Browse
5 results
Search Results
Item Locating open-channels in octagon networks on chip-microprocessors(IEEE Computer Society help@computer.org, 2020) Bhowmik, B.; Biswas, S.; Deka, J.K.; Bhattacharya, B.B.Networks-on-chip (NoCs) provide the essential communication infrastructure for building today's on-chip multiprocessors. Albeit mesh is commonly used as the underlying interconnection architecture, other regular topologies such as octagons or spidergons, find recent applications to hybrid, small-world, and smart networks. Aggressive technology scaling, however, makes NoCs susceptible to manufacturing defects and causes failures in their operations. This paper presents a distributed, on-line built-in-self-test (BIST) mechanism that targets open faults on communication channels in an octagon NoC. We introduce a novel test scheduling scheme that exploits the knowledge of multithreading for reducing the overall test time with minimal degradation of performance. We evaluate the proposed test scheme for a 16-bit octagon NoC and report experimental results. © 2020 IEEE.Item Improving Reliability in Spidergon Network on Chip-Microprocessors(Institute of Electrical and Electronics Engineers Inc., 2020) Bhowmik, B.; Deka, J.K.; Biswas, S.Aggressive technology scaling continues to make networks-on-chip (NoCs) vulnerable to failures that relentlessly result in reliability concerns and unexpected system performance degradation. Therefore, there is an urgent demand for an effective test methodology that does not only improve the NoC's reliability but also prevent the system from being trapped into system-level failure modes. This paper presents a low-cost test scheme that addresses stuck-at faults in the communication channels of a Spidergon NoC. A built-in-self-test (BIST) method is presented to quickly detect the faults and reduce the affected application packets. The present test method is combined with a scheduling technique that together minimizes the test cost metrics, e.g., reduces 81.25% test time making the current test solution to become at least 5× faster. Furthermore, the solution shows less influence on system performance. © 2020 IEEE.Item Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels(Institute of Electrical and Electronics Engineers Inc., 2020) Bhowmik, B.; Biswas, S.; Deka, J.K.With the continuous growth in wire density, the reliability has become a dominant burden while channels of a modern NoC are exposed to various faults. A key requirement for the NoC is therefore to propose a mechanism that can account for a channel fault since it significantly impacts NoC performance. This paper presents a distributed test strategy that detects and diagnoses logic-level faults coexist in NoC channels and deeply analyze the severe impact of these faults on network performance. Fault coexistence in channels makes a fraction undetectable and is addressed here. Simulation results demonstrate the effectiveness of the proposed strategy. © 2020 IEEE.Item Reliability Monitoring in a Smart NoC Component(Institute of Electrical and Electronics Engineers Inc., 2020) Bhowmik, B.; Deka, J.K.; Biswas, S.SMART NoC topology components, such as octagon, spidergon are progressively becoming the primary design choice for implementing the communication backbone in a multi-core SoC platform for lowering a high number of inter-router hops required by long-range traffic. However, aggressive technology scaling has increased the number of transient/permanent faults raising the reliability concerns in a SMART NoC. This paper presents a reliability monitoring scheme for addressing channel-short faults in the basic octagon NoC. Along with the online detection and diagnosis of short faults, an effective scheduling scheme is proposed to provide a low-cost test solution that outperforms over a set of prior schemes. © 2020 IEEE.Item Selective Fault-Masking for Improving Yield and Performance of On-Chip Networks(Institute of Electrical and Electronics Engineers Inc., 2021) Bhowmik, B.; Deka, J.K.; Biswas, S.Nowadays, the reliability in network-on-chip (NoC) has become a crucial issue that leads to network performance degradation. Built-in-self-test (BIST) is one of the primary test schemes often used to achieve high reliability. The scheme allows a frequent test of and recovery from faults experienced on an NoC's fundamental component, e.g., communication channels. This paper presents a BIST approach that detects open and short faults in communication media to demonstrate the fault-masking phenomenon. The phenomenon as the self-repairing mode of the communication media improves the yield and performance of the NoCs. Rigorous simulations are made on an 8×8 mesh NoC with faulty and repaired channels. Results reveal that allowing faults in communication tracks degrades the network performance up to 30% while the self-repairing mode improves nearly 75%. © 2021 IEEE.