Conference Papers
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/28506
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Item A 28-32GHz CMOS LNA with broadband approach for 5G Mm-wave communication cells(Institute of Electrical and Electronics Engineers Inc., 2019) Vignesh, R.; Gorre, P.; Kumar, S.; Song, H.This paper first time reports a wideband low noise amplifier (LNA) with achievable minimum atmospheric absorption frequency band for 5G millimeter wave communication cells. A novel suspended substrate line based parallel-series network is optimized and analyzed that demonstrates a wideband response. The proposed LNA consists of two stage Cascode topology with incorporated parallel-series network and microwave components that provides broadband ranging from 28GHz to 32GHz. A full of two stage Cascode LNA overcoming the traditional mismatching constraints with consideration of suspended substrate lines (SSL) and Tee-junction in the proposed design. It is observed that suspended lines reduce parasitic and bulk effects of devices and enables LNA to provide broadband communication for 5G macro and micro cells. The proposed design is realized using RF 65nm Magna Hynix CMOS process with layout cell. The simulation results reveals that 28GHz-32GHz wide band with maximum forward gain of 25dB. The minimum noise figure of 2.5dB is achieved with optimization of passive components. The input impedance (real and imaginary) and smith chart realization for LNA provides satisfactory performance. © 2019 IEEE.Item Performance of X-Band CMOS LNA with Broadband Approach for 5G Wireless Networks(Springer Science and Business Media Deutschland GmbH, 2021) Pottem, S.K.; Kabade, R.D.; Nikith, T.N.; Mondal, S.; Kumar, S.This paper presents a CMOS low noise amplifier (LNA) for X-band range of communication for 5G wireless networks. The proposed LNA consists of three stages of casade–cascode CS topology. A Chebyshev filter T-network stage is employed for broadband input impedance matching while cascode–cascade stage is followed for a higher gain. The current mirror topology is used to provide bias current and active load to the LNA. The LNA is designed and simulated using 180 nm UMC Taiwan process in cadence platform. The proposed schematic simulation achieved a gain higher than 15 dB for the range of 8 GHz to 12 GHz (X-Band) and a minimum noise figure (NF) of 4.2 dB at 12 GHz. The proposed differential LNA operates under 2 V power supply and layout using metal–insulator–metal layers. The design and layout are verified using DRC and LVS rules. © 2021, Springer Nature Singapore Pte Ltd.Item High Gain Ultra-Low NF Wideband CMOS Low Noise Amplifier Design Using 2-Stage Series-Parallel LC Matching Network(Institute of Electrical and Electronics Engineers Inc., 2023) Sudhanva, P.V.C.S.; Yugandhar, B.; Kumar, S.; Kumar, K.; Bhat, K.G.The focus of this work is the development of a sub-6 GHz (2-6 GHz) low noise amplifier (LNA) for 5G applications, using a 65 nm CMOS process. A novel two stage common source (CS) cascode source degeneration LNA topology by incorporating a contemporary series parallel LC network and two stage LC network for input and output matching respectively is proposed. The circuit implementation, simulations and evaluation of the LNA's performance are done utilizing the RF Spectre Cadence Virtuoso. According to the evaluation results, the LNA dissipates a total power of 19.6 mW at the supply voltage of 0.7 V. It offers an operational wide bandwidth (BW) of 3.2 GHz which ranges from 2.8 GHz to 6 GHz. The LNA has a peak gain of 36 dB and minimum noise figure (NF) of 1.1 dB across the sub-6 GHz spectrum. The proposed LNA also performs well in terms of stability and linearity measures. The layout of the proposed LNA occupies an area of 0.182mm2 © 2023 IEEE.