High Gain Ultra-Low NF Wideband CMOS Low Noise Amplifier Design Using 2-Stage Series-Parallel LC Matching Network

Abstract

The focus of this work is the development of a sub-6 GHz (2-6 GHz) low noise amplifier (LNA) for 5G applications, using a 65 nm CMOS process. A novel two stage common source (CS) cascode source degeneration LNA topology by incorporating a contemporary series parallel LC network and two stage LC network for input and output matching respectively is proposed. The circuit implementation, simulations and evaluation of the LNA's performance are done utilizing the RF Spectre Cadence Virtuoso. According to the evaluation results, the LNA dissipates a total power of 19.6 mW at the supply voltage of 0.7 V. It offers an operational wide bandwidth (BW) of 3.2 GHz which ranges from 2.8 GHz to 6 GHz. The LNA has a peak gain of 36 dB and minimum noise figure (NF) of 1.1 dB across the sub-6 GHz spectrum. The proposed LNA also performs well in terms of stability and linearity measures. The layout of the proposed LNA occupies an area of 0.182mm2 © 2023 IEEE.