Conference Papers

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Author: search.filters.author.Kumar, S.Subject: search.filters.subject.CMOS

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    High Gain Ultra-Low NF Wideband CMOS Low Noise Amplifier Design Using 2-Stage Series-Parallel LC Matching Network
    (Institute of Electrical and Electronics Engineers Inc., 2023) Sudhanva, P.V.C.S.; Yugandhar, B.; Kumar, S.; Kumar, K.; Bhat, K.G.
    The focus of this work is the development of a sub-6 GHz (2-6 GHz) low noise amplifier (LNA) for 5G applications, using a 65 nm CMOS process. A novel two stage common source (CS) cascode source degeneration LNA topology by incorporating a contemporary series parallel LC network and two stage LC network for input and output matching respectively is proposed. The circuit implementation, simulations and evaluation of the LNA's performance are done utilizing the RF Spectre Cadence Virtuoso. According to the evaluation results, the LNA dissipates a total power of 19.6 mW at the supply voltage of 0.7 V. It offers an operational wide bandwidth (BW) of 3.2 GHz which ranges from 2.8 GHz to 6 GHz. The LNA has a peak gain of 36 dB and minimum noise figure (NF) of 1.1 dB across the sub-6 GHz spectrum. The proposed LNA also performs well in terms of stability and linearity measures. The layout of the proposed LNA occupies an area of 0.182mm2 © 2023 IEEE.
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    A L/S/C/X/Ku-Band Three-Stack, Two stages Fully Integrated CMOS Power Amplifier with 20.9 % PAE Using T-Network
    (Institute of Electrical and Electronics Engineers Inc., 2023) Kumar, K.; Kumar, S.; Gupta, M.P.
    This work proposes an L/S/C/X/Ku-Band three-stack two stages fully integrated CMOS power amplifier (PA) that realized in 65nm and achieves high efficiency, high output power over wide impedance bandwidth from 2-20 GHz. The proposed PA circuit comprises of T-network broadband input power match design, interstage tuning network and output power stage. The interstage tuning network is employed to achieve an excellent gain (|S21|) flatness of 16.3 ± 0.9 dB. The proposed PA design is employed 3-stack of transistor under supply of 3V at stage-1 followed LC and stage-2 to achieve high output power. The load pull analysis is performed to optimize the T- type output matching network for achieving PAE of 20.9 % and output power of 15.97 dBm at 7 GHz with 50 Ω load impedance. Besides, this PA provides 1 dB output compression point of 11.2 ± 0.8 dBm over full frequency band and also achieves the output third order intercept point of 23.2 dBm at 7 GHz using two tone signal. © 2023 IEEE.