Conference Papers

Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/28506

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Author: search.filters.author.Bhowmik, B.Subject: search.filters.subject.Network-on-Chip

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    Topology Exploration for Long-Distance Communication
    (Institute of Electrical and Electronics Engineers Inc., 2021) Gagan, N.; Bhowmik, B.
    With the increase in the network size, the conventional network-on-chip (NoC) imposes high latency due to the lack of shorter paths between far nodes resulting in performance degradation. This paper proposes an alternative approach that improves performance for long-distance communication in a mesh NoC. The proposed method explores a new topology named 'pseudo-3D mesh' in which a few new nodes are added in the upper layer of a 2D mesh NoC. Experimental results show that the proposed scheme provides acceptably high performance at the cost of little hardware over-head. © 2021 IEEE.
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    LR-Based Performance Evaluation of MoCs
    (Institute of Electrical and Electronics Engineers Inc., 2024) Hazarika, P.; Bhowmik, B.
    In the recent decade, on-chip communication net-works have developed into a potent platform for tackling chal-lenging and significant computation issues. However, many applications cannot achieve high-performance communication needs due to the seamless integration of computing cores in systems-on-chip (SoCs). Subsequently, a network-on-chip (NoC) has emerged as a prominent on-chip communication infrastructure in SoCs. Performance analysis of NoC's is essential for its architectural design and is traditionally evaluated employing a simulator. How-ever, simulation-based performance evaluation is relatively slow and may take a long time with varying architectural NoC sizes. This paper presents an AI-based approach for investigating mesh-based NoC (MoC) performance over the traditional simulation-based performance evaluation. The proposed framework targets to reach two objectives- quickly and accurately evaluation of various NoC performance metrics. Simulations are performed at varying architectural setups on a set of mesh NoCs to generate the training dataset for the proposed framework. Consequently, the framework satisfactorily predicts different performance metrics. For example, network and packet latency; hop count; switch, channel, and total power consumption; and total area are in the range of 58.14-88.49 and 58.69-106.97 cycles; 6.231-6.257; 1.44-13.02, 13.73-129.06, and 25.26- 177.44 μ W; and 1.35874 μ m2, respectively while the proposed framework is applied on the 9 x 9 mesh NoC. The metrics are with 94% accuracy and predicted at very significantly less time. The LR model saves 99.45 % evaluation time resulting in the speedup of 260 x than a simulation - based method. © 2024 IEEE.
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    EFH - An Efficient Fault-Tolerant Routing Methodology for 2D Mesh NoCs
    (Institute of Electrical and Electronics Engineers Inc., 2025) Bhowmik, B.; Girish, K.K.; Raju, A.J.; Chakraborty, R.
    The increasing complexity of modern System-on-Chip (SoC) designs demands reliable and scalable communication frameworks. Network-on-Chip (NoC) architectures, particularly the 2D Mesh topology, have gained prominence due to their structured layout and scalability, facilitating efficient data routing among interconnected functional blocks. However, the 2D Mesh topology remains highly vulnerable to static and dynamic faults, which disrupt network performance and increase congestion. Existing fault-tolerant routing algorithms struggle with handling complex fault patterns, such as concave and irregular fault regions, leading to increased latency and packet loss. This paper introduces the Entrance, First, Hole (EFH) routing methodology, which employs a dynamic node-labeling strategy to classify nodes into entrance, first, and hole nodes. This classification enables the network to bypass faults, maintain functional nodes, and optimize routing paths without introducing significant overhead. Experimental results using the Noxim NoC simulator demonstrate that EFH significantly enhances network throughput, reduces latency, and improves overall fault resilience compared to existing approaches. © 2025 IEEE.