Conference Papers
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Item Improved tri-gate FinFET transistor with InGaAs(Institute of Electrical and Electronics Engineers Inc., 2017) Sharma, B.S.; Bhat, M.S.Inclusion of the III-V semiconductors in Field Effect Transistor technology is frequent, now days. In this paper, a tri-gate FinFET using InGaAs is proposed. Current carrying capability of the FinFET is usually large, since tri-gate structure, hence an appropriate doping in the channel would improve the ON and OFF characteristics of the device. To get an excellent ION/Ioff, doping concentration in the channel and source/drain region is varied according to material requirements. Channel length Lg of the proposed device is 20 nm. With high-K dielectric H fO2 as oxide, metal gate-oxide stack in the FinFET is designed and simulations are performed. Simulation of FinFET with gate-oxide thickness tox = 1 nm and a channel width Wc = 10nm, exhibits Ion/Ioff = 10.801 × 103, subthreshold slope SS ≈ 62 mV/decade and drain-induced-barrier-lowering DIBL = 83.3 mV/V. © 2017 IEEE.Item Design of high performance dual-gate nano-scale In0.55Ga0.45 as transistor with modified substrate geometry(Institute of Electrical and Electronics Engineers Inc., 2017) Sharma, B.S.; Bhat, M.S.Structures based on Indium Gallium Arsenide (InGaAs) have attracted a lot of attention in Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology, recently. In this paper, we investigate the performance of a nano scale dual-gate MOSFET using InGaAs, and propose the design of a high performance In0.55Ga0.45As transistor with modified substrate geometry. Impact of changing the mole-fraction 'x' in In1-xGaxAs on the device performance is observed. To achieve best performance, the device geometry, relative mole fraction of In & Ga, the doping concentration of source/drain region and channel stop implant are varied. Simulations are performed to obtain output and transfer characteristics considering a N+ poly gate as well as a metallic (Al) gate for the proposed device. Simulations show excellent subthreshold slope (~ 62mV/dec), DIBL (~ 30 m V/V) and ION/IOFF = 2.23 × 106 values. As an application, an inverter is designed using this device and its DC and Transient responses for resistive and saturated enhancement NMOS load are plotted. © 2017 IEEE.Item A novel dual-gate nano-scale InGaAs transistor with modified substrate geometry(Institute of Electrical and Electronics Engineers Inc., 2017) Sharma, B.S.; Bhat, M.S.Structures based on Indium Gallium Arsenide (InGaAs) have attracted a lot of interest in Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) technology recently. In this paper, a new nano-scale dual-gate MOSFET using In0.75 Ga0.25As is proposed. Multiple designs were simulated with different doping concentration in the source/drain region and the channel stop region to get an excellent Ion/Ioff. Since current in Metal-Oxide-Semiconductor (MOS) depends on the doping profile of the channel, a careful re-engineering of the channel would improve the MOSFET characteristics. Channel length, Lg of the proposed device is 20 nm which produces a significant amplification and supports large current due to wide channel interaction. Simulation of In0.75 Ga0.25 As MOSFET with Lg = 20 nm, gate-oxide thickness toxGate1 = toxGate2 = 2nm and a width Z = 1000nm, exhibits transconductance gm-max ≈ 293.626 μS/μm, subthreshold slope SS ≈ 70 mV/decade and drain-induced-barrier-lowering DIBL = 41.66 mV/V. © 2017 IEEE.