Improved tri-gate FinFET transistor with InGaAs
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Date
2017
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
Institute of Electrical and Electronics Engineers Inc.
Abstract
Inclusion of the III-V semiconductors in Field Effect Transistor technology is frequent, now days. In this paper, a tri-gate FinFET using InGaAs is proposed. Current carrying capability of the FinFET is usually large, since tri-gate structure, hence an appropriate doping in the channel would improve the ON and OFF characteristics of the device. To get an excellent I<inf>ON</inf>/I<inf>off</inf>, doping concentration in the channel and source/drain region is varied according to material requirements. Channel length L<inf>g</inf> of the proposed device is 20 nm. With high-K dielectric H fO<inf>2</inf> as oxide, metal gate-oxide stack in the FinFET is designed and simulations are performed. Simulation of FinFET with gate-oxide thickness t<inf>ox</inf> = 1 nm and a channel width W<inf>c</inf> = 10nm, exhibits I<inf>on</inf>/I<inf>off</inf> = 10.801 × 103, subthreshold slope SS ≈ 62 mV/decade and drain-induced-barrier-lowering DIBL = 83.3 mV/V. © 2017 IEEE.
Description
Keywords
FinFET, InGaAs FinFET, Nano InGaAs Device, Short Channel FinFET, Thin MOS
Citation
Proceedings of 2017 International Conference on Innovations in Information, Embedded and Communication Systems, ICIIECS 2017, 2017, Vol.2018-January, , p. 1-5
