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The problem of mapping synthesized RTL structures onto look-up table (LUT)-based field programmable gate arrays (FPGA's) is addressed in this paper. The key distinctive feature of this work is a novel approach to perform the mapping by utilizing the iterative nature of the data path components. The approach exploits the regularity of data path components by slicing the components and mapping slices of one or more connected components together. This is in contrast to other FPGA mapping techniques which start from Boolean networks. Both cost optimal and delay optimal mappings are supported. The objective in cost optimal mapping is to cover a given data path network with minimum number of CLB's. Similarly in delay optimal mapping, the objective is to reduce the number of CLB levels in the critical combinational logic paths. Implementation of these mapping techniques with LUT based FPGA's as target technology results in a significant reduction in cost (CLB count) and critical path delays (CLB levels). © 1998 IEEE.
(Direct mapping of RTL structures onto LUT-based FPGA's) Naseer, A.R.; Balakrishnan, M.; Kumar, A.
1998
An FPGA and ASIC Implementation of Cubing Architecture
(Springer, 2022) Naresh Kumar Reddy, B.N.K.; Seetharamulu, B.; Siva Krishna, G.S.; Vani, B.V.
The optimization of VLSI design is playing an important role in the development of technological applications. The optimization of VLSI technology helps to increase the performance and speed of the processors. Cubing is an optimization technique in which numerous computations are performed quickly. In this paper proposes a technique for the implementation of cubing. By using the proposed method, the complexity of the multiplication of numbers for cubes is reduced. The proposed architecture is synthesized and simulated using Vivado design suit 2018.3 and implemented on a Kintex-7 FPGA board. The Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 cadence tool is used in an application specific integrated circuit platform. Compared with the results obtained with well-known cubing architectures, the proposed method is used to improve the performance, and decrease the power consumption and area of processors. © 2022, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
Design and implementation of a signal processing ASIC for digital hearing aids
(Elsevier B.V., 2022) Deepu, D.; Ramesh Kini, R.K.; Sumam David, S.
People with hearing loss can be benefited from assistive devices like hearing aids. This article presents the implementation of a signal processing chip for digital hearing aid applications. The functionality of the proposed design was tested in real-time using two field programmable gate arrays (FPGAs), one of them modeled as a hearing aid processor and the other as an external audio CODEC. The hearing aid processor contains an 18-band 1/3-octave ANSI S1.11 filter bank, which performs the audiogram compensation and a dynamic range compression algorithm to restrict the output signal to an acceptable loudness. The functionality of an external audio CODEC was replicated in the other FPGA to act as the analog front end circuit of a hearing aid. Serial Peripheral Interface (SPI) was used for communication between the two FPGAs. The SPI protocol was modified to make the hearing aid programmable through the data in line of the interface itself. The proposed hearing aid chip was implemented using standard cell based design flow with a 5x5 mm fixed die size intended to fit in a 48-pin package. © 2022 Elsevier B.V.

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