An FPGA and ASIC Implementation of Cubing Architecture

Abstract

The optimization of VLSI design is playing an important role in the development of technological applications. The optimization of VLSI technology helps to increase the performance and speed of the processors. Cubing is an optimization technique in which numerous computations are performed quickly. In this paper proposes a technique for the implementation of cubing. By using the proposed method, the complexity of the multiplication of numbers for cubes is reduced. The proposed architecture is synthesized and simulated using Vivado design suit 2018.3 and implemented on a Kintex-7 FPGA board. The Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 cadence tool is used in an application specific integrated circuit platform. Compared with the results obtained with well-known cubing architectures, the proposed method is used to improve the performance, and decrease the power consumption and area of processors. © 2022, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.