Design and implementation of a signal processing ASIC for digital hearing aids

Abstract

People with hearing loss can be benefited from assistive devices like hearing aids. This article presents the implementation of a signal processing chip for digital hearing aid applications. The functionality of the proposed design was tested in real-time using two field programmable gate arrays (FPGAs), one of them modeled as a hearing aid processor and the other as an external audio CODEC. The hearing aid processor contains an 18-band 1/3-octave ANSI S1.11 filter bank, which performs the audiogram compensation and a dynamic range compression algorithm to restrict the output signal to an acceptable loudness. The functionality of an external audio CODEC was replicated in the other FPGA to act as the analog front end circuit of a hearing aid. Serial Peripheral Interface (SPI) was used for communication between the two FPGAs. The SPI protocol was modified to make the hearing aid programmable through the data in line of the interface itself. The proposed hearing aid chip was implemented using standard cell based design flow with a 5x5 mm fixed die size intended to fit in a 48-pin package. © 2022 Elsevier B.V.