Browsing by Author "Rao, R."

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A Comparative Analysis of Asynchronous and Synchronous NoC for Dynamic Traffic Handling using trace-inspired Synthetic Multimedia Data
(Institute of Electrical and Electronics Engineers Inc., 2024) Saranya, M.N.; Avinash, C.T.; Rao, R.
The paper investigates the feasibility of asynchronous Network-on-Chip (NoC) with wormhole switching in supporting traffic with variable data rates. A new approach to generate synthetic traffic close to realistic multimedia data traffic is also presented for the first time. This multimedia data stream traffic is utilized to evaluate the dynamic traffic handling capability of a generic synchronous NoC switch and asynchronous NoC switch architectures. Multimedia data streams are characterized as variable bit rate data streams where the amount of data being transmitted changes dynamically, depicting the heterogeneous timing of modern System-onChip (SoC). The Cadence Spectre Analog/Mixed Signal (AMS) Designer tool is used as a verification platform for the ease of simulation and to draw a fair comparison between the two architectures. The simulation platform is augmented with a real-time multimedia data stream for analysis. The simulation results show that the asynchronous design, activated only upon receiving data, outperforms the clock-triggered synchronous design in variable data-driven scenarios. Â© 2024 IEEE.
A Full-Swing, High-Speed, andÂ High-Impedance Hybrid 1-Bit Full Adder
(Springer Science and Business Media Deutschland GmbH, 2023) Malkhandi, C.; Rao, R.
In this paper, an attempt has been made to design a high-speed architecture for a 1-bit full adder. The proposed circuit uses a hybrid structure that combines CMOS logic and Transmission gate logic for design and implementation. Using both CMOS and Transmission gate logic in a design can provide the advantages of both the logic design. The SPICE simulations for the proposed full adder circuit have been performed with TSMC 180Â nm CMOS Technology. The proposed full adder circuit has 23.63% less carry delay than the sum delay, which can be exploited for use in more complex systems like multi-bit adders where the carry path becomes the critical path. The speed of the proposed full adder is found to improve by 32.6% and 8.03% for sum and carry, respectively, with respect to CMOS implementation and by 1.62% and 21.02% with respect to some of the best-reported architectures in the literature. The proposed circuit has been found to have high input impedance and a low output impedance along with a full swing of voltages at the output. Â© 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
A High Performance Early Acknowledged Asynchronous Pipeline using Hybrid-logic Encoding
(Elsevier B.V., 2020) Girija Sravani, K.; Rao, R.
This paper details a novel asynchronous pipelining methodology that maximizes the throughput buffering capacity and robustness of gate-level pipelined systems. The data paths in the proposed pipeline style are encoded using hybrid logic encoding scheme, which incorporates simplicity of the single-rail encoding and robustness of the dual-rail encoding. The control path that provides the synchronization between pipeline stages is constructed based on the simple and high-speed early acknowledgment protocol. Further, the proposed pipeline accommodates isolate phase to achieve 100% storage capacity. Two test cases: A 4-bit,10-stage FIFO and a 16-bit adder, have been designed in 90 nm technology to validate the proposed pipeline style. The FIFO has been laid out in the UMC 180 nm process using the cadence tool suite. The post-layout results of FIFO show 12.5% better throughput than the high capacity single-rail pipeline. Simulation results of the adder also reveal that the proposed structure achieves the throughput of 3.44 Giga-items/sec, which is 44.18% higher than the APCDP (Asynchronous pipeline based on constructed critical path) and 11.9% higher than the high capacity single-rail pipelines. © 2019 Elsevier B.V.
A new blood pressure prediction method using wrist pulse examination
(Springer, 2020) Sukesh Rao, M.; Rao, R.
Wrist pulse examination plays an imperative role in clinical practice including contemporary medicine systems like Ayurveda. Wrist pulse measurement system can also be used for blood pressure (BP) monitoring. This article proposes an extension of wrist pulse analysis system for BP monitoring. Wrist pulse signals are captured using three piezoelectric thin film sensors at the radial artery of the wrist as per Ayurvedic pulse diagnosis method. The wave features such as Spatial Pulse Transit Time (SPTT) and Spatial Pulse Wave Velocity (SPWV) are extracted from the captured wrist pulses. Pearson’s correlation coefficient is computed to find the correlation between SPTT and BP measured using standard measuring instrument (Omron HEM-6131). A moderate correlation is found between SPTT and Systolic Blood Pressure (SBP) with correlation coefficient of 0.72. SPWV values computed from SPTT are used to develop an empirical model for BP in terms of SPWV. Limitations of the empirical model lead to a theoretical model using Poiseuilli law. The Mean Artery Pressure (MAP) using theoretical model is recorded for 41 participants. The deviation of MAP thus computed as compared to the readings taken from clinically validated BP monitoring device is found to be varying in the range of 4.5 ± 2.3 mmHg. © 2020, IUPESM and Springer-Verlag GmbH Germany, part of Springer Nature.
A reliability test for the body constitution diagnosis using wrist pulse analysis based on ayurveda
(National Institute of Science Communication and Policy Research, 2022) Sukesh Rao, M.; Ravishankar, K.; Rao, R.
Wrist pulse diagnosis is the most primitive and apparent way to know about the human body condition for the diagnosis of disease. Ayurveda, an ancient Indian science, introduced wrist pulse diagnosis in the name of 'Nadi'. Due to the lack of expertise and standardisation, the knowledge of Nadi is limited to very few Ayurvedic practitioners. An automated wrist pulse reading instrument can overcome this problem and help in non-invasive diagnosis using a wrist pulse based on Ayurveda. The primary objective of the research is to develop instrumentation to digitise the three pulse patterns viz., Vata (V), Pitta (P) and Kapha (K). Based on the signals acquired, the nature of the body (Prakriti) is identified and categorised into different classes. Wrist pulses are acquired using three thin-film flexible piezoelectric sensors and processed using a signal conditioning circuit. Signals are quantised using data acquisition module and processed. The studies carried out in the present work show substantial to moderate (based on the number of classes considered) agreement in the pulse-based classifications done by expert Ayurvedic physician and the developed instrument. Cohen's kappa of 0.719 and 0.454 are obtained as inter-rater reliability between traditional and instrumental readings on wrist pulse taken on basic level (VPK) and sub-levels (VP, VK PK). An inter-rater reliability test using Cohen's Kappa is adopted for this purpose. Similarly, reliability between Ayurvedic questionnaire-based and wrist pulse-based Prakriti identification are also tested. A Cohen's kappa of 0.587 and 0.476 is obtained between Prakriti and two different pulse reading data sets with basic level of classification viz. instrument and traditional method. © 2022, National Institute of Science Communication and Policy Research. All rights reserved.
An Exploration of the Effective Path for Current Conduction in a Triple Gate Junctionless FinFET
(Institute of Electrical and Electronics Engineers Inc., 2023) Chennamadhavuni, S.; Mathew, S.; Rao, R.
The goal of this work is to exclusively investigate the effective path for current conduction in the channel of a Triple Gate (TG) Silicon-ON-Insulator (SOI) Junctionless Fin Field Effect Transistor (JLFinFET). It is observed that various structural parameters play a key role in deciding the location of the effective current path both in full depletion mode and partial depletion mode in TG SOI JLFinFET. Considering the present day technology requirements 20 nm was chosen as the gate length. Simulations performed using 3-D TCAD namely ATLAS by Silvaco Inc. reveal that the conducting path from source to drain starts from nearer to the centre of the channel (i.e, at half the fin height and half the fin width) when the transistor switches from the OFF state to the ON state. It is also observed that when the triple gate transistor scales down in size the capacitive coupling between the top gate and side gates is a crucial factor in determining the location of the effective current path. Â© 2023 IEEE.
An improved Fourier series-based analytical model for threshold voltage and sub-threshold swing in SOI junctionless FinFET
(Elsevier Ltd, 2024) Mathew, S.; Chennamadhavuni, S.; Rao, R.
In this work, Fourier series-based analytical models for threshold voltage (Vth) and Sub-threshold Swing (SS) are developed for Junctionless Fin Field Effect Transistor (JLFinFET) on Silicon On Insulator (SOI) substrate, taking into account the location of the onset of current conduction in the channel. Rigorous simulations were conducted to analyse the current conduction path when JLFinFET surpasses the threshold voltage. Based on the findings from these simulations, threshold voltage condition used for deriving the threshold voltage model is modified. This modified model gives a better prediction of Vth for JLFinFET than the already existing model which doesn't include approximations based on the location of onset of current conduction. The analytical model developed for SS is also capable of closely predicting the SS of JLFinFET obtained from the TCAD simulator down to a gate length of 20 nm. © 2024 Elsevier Ltd
Damage Analysis of Tool-Based Micromachining Setup Using Electrical Continuity-Based Contact Detection System
(Springer, 2021) Veeresha, R.K.; Rao, M.; Rao, R.; Sushith, S.; Karegoudra, M.K.
Initial registration of tool with respect to workpiece is a critical requirement in tool-based micromachining setup. As the tool is in the order of few hundred micrometre diameter and rotating at very high speed, hence, the chance of tool breakage or workpiece surface damage during tool workpiece registration is more during micromachining. Initial tool registration of tool with respect to workpiece circuit was developed and incorporated with developed tool-based micromachining setup. The performance of the developed electrical continuity-based contact detection circuit was done by feeding the workpiece with different offset dimensions. From the experiments, it’s observed that there is more damage in workpiece when tool workpiece offset distance is more in both milling and drilling tools. © 2021, ASM International.
DDCVS Logic for Asynchronous Gate-Level Pipelined Circuits
(Springer Science and Business Media Deutschland GmbH, 2021) Girija Sravani, K.; Rao, R.
This paper proposes a new way of realizing the data paths for asynchronous domino logic gate-level pipeline styles. This novel approach improves the speed of the pipelines by preserving the latch-less feature of domino pipelines. In this work, the data paths of three asynchronous 16-bit adders based on APCDP, LP2/2, and HC-Hybrid pipelines are constructed using dual-rail domino cascode voltage switch (DDCVS) logic and simulated using cadence toolset in 90Â nm technology. The adders based on DDCVS logic have exhibited higher performance and lower energy-delay square product compared to the adders based on domino logic. Â© 2021, Springer Nature Singapore Pte Ltd.
Design and simulation of high pressure piezohydraulic pump with active valves
(2016) Muralidhara, S.N.; Rao, R.
Pumps incorporated with active valves provide active control on both the inlet and outlet valves. Here piezoelectric actuation is used as the actuation system since piezoelectric actuators can produce controlled actuation. Also piezoelectric actuators can produce high displacement with large force and has advantages such as high resolution, fast response, high stability, high reliability, compactness etc. In this work active valves are designed for a high pressure piezo-hydraulic pump. Flexural amplifiers for piezoelectric actuators are designed for the valve diaphragm actuation as well as for the pumping diaphragm actuation. There are three slotted diaphragms designed and operated by three separate flexurally amplified piezoelectric actuators. The flexural amplifiers and the diaphragms are analysed using ANSYS analysis software. Suitable mathematical model is developed using MATLAB software for synchronizing the sequence of actuation with respect to timing. Here Bouc-Wen model is made use for modelling the hysteresis effect. MATLAB Simulink is used to develop the model and simulations are performed to determine the displacement produced by the piezoelectric actuators when applied with a voltage. Also simulations are carried out for the determination of pumped volume, flow rate and stroke length of a particular cylinder. � 2016 IEEE.
Design and simulation of high pressure piezohydraulic pump with active valves
(Institute of Electrical and Electronics Engineers Inc., 2016) Rao, S.N.; Rao, R.
Pumps incorporated with active valves provide active control on both the inlet and outlet valves. Here piezoelectric actuation is used as the actuation system since piezoelectric actuators can produce controlled actuation. Also piezoelectric actuators can produce high displacement with large force and has advantages such as high resolution, fast response, high stability, high reliability, compactness etc. In this work active valves are designed for a high pressure piezo-hydraulic pump. Flexural amplifiers for piezoelectric actuators are designed for the valve diaphragm actuation as well as for the pumping diaphragm actuation. There are three slotted diaphragms designed and operated by three separate flexurally amplified piezoelectric actuators. The flexural amplifiers and the diaphragms are analysed using ANSYS analysis software. Suitable mathematical model is developed using MATLAB software for synchronizing the sequence of actuation with respect to timing. Here Bouc-Wen model is made use for modelling the hysteresis effect. MATLAB Simulink is used to develop the model and simulations are performed to determine the displacement produced by the piezoelectric actuators when applied with a voltage. Also simulations are carried out for the determination of pumped volume, flow rate and stroke length of a particular cylinder. Â© 2016 IEEE.
Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems
(Springer, 2024) Saranya, M.N.; Rao, R.
The increasing multi-core system complexity with technology scaling introduces new constraints and challenges to interconnection network design. Consequently, the research community has a converging trend toward an asynchronous design paradigm for Network-on-Chip (NoC) architecture as a promising solution to these challenges. This paper addresses the design and functional verification aspects of an asynchronous NoC router microarchitecture for a Globally Asynchronous Locally Synchronous (GALS) system. Firstly, the paper introduces a novel mixed-level abstract simulation approach for faster functional verification of the asynchronous architecture using the commercially available Spectre Analog and mixed-signal simulation (AMS) Designer tool. This simulation methodology intends to ensure the feasibility of the design and identify shortcomings, if any, before the subsequent implementation stages of the design. Also, the paper proposes a new baseline asynchronous router built on a domino logic pipeline template with a novel hybrid encoding scheme. The new hybrid encoding scheme facilitates simple architecture with no additional timing constraints. The proposed verification methodology evaluates the baseline asynchronous router’s functional verification in Cadence’s AMS designer tool. Preliminary simulation results conform to the objectives of the paper. Further, the same verification setup establishes the design validation in subsequent stages of the design implementation. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.
Design of Asynchronous Circular FIFO Buffer for Asynchronous Network on Chips
(Institute of Electrical and Electronics Engineers Inc., 2022) Chaturvedi, S.; Saranya, M.N.; Rao, R.
Network on Chip is employed for on-chip communication in multicore System-on-Chips for its advantages over bus-based architectures, more so with reducing feature size. The NoC implementation can be synchronous, asynchronous or Globally Asynchronous Locally Synchronous (GALS). However, synchronous design performance is limited by the global clock rate and depends on the slowest critical path, making it indispensable to optimize all portions of the design. Asynchronous design avoids clock skew and clock distribution issues on the chip and allows flexibility in the optimization of the rarely used portions of the system. Along with the benefit of reduced power consumption, they perform better in terms of delays, yielding average-case performance, as opposed to the worst-case performance yielded by the synchronous counterpart. One of the integral parts of NoC routers is buffers. In this paper, an asynchronous four-stage FIFO buffer based on domino logic and a synchronous four-stage FIFO buffer for comparison have been simulated using LTSpice on the TSMC 180nm technology. Results show that the proposed asynchronous design consumes 50% lesser power than the synchronous design, while maintaining a comparable performance in terms of latency and throughput. Â© 2022 IEEE.
Design of Dual-Material Gate Junctionless FinFET based on the Properties of Materials Forming Gate Electrode
(Taylor and Francis Ltd., 2024) Mathew, S.; Bhat, K.N.; Nithin; Rao, R.
This work elaborately investigates the electrical behaviour and short channel performance of Dual-Material Gate Junctionless Fin Field Effect Transistors (DMG-JLFinFETs) with multiple-gate metal pairs and varying gate metal length ratios. Rigorous analysis on the nature of DMG-JLFinFET with gate length as low as 10 nm is done using a device simulator by Silvaco, Inc. The gate material closer to the source, namely M1, has a dominating influence on the threshold voltage (Vth) and tunnelling current (Itunn) than the gate material closer to the drain (named M2) in a DMG-JLFinFET. Itunn is lower when the work function of M1 (ΦM1) is greater than the work function of M2 (ΦM2). The relative change in threshold voltage is minimum for Platinum–Gold (PtAu)-DMG-JLFinFET (0.68%). Titanium–Aluminium (TiAl) and Nickel–Titanium (NiTi) gate material pairs, having the same work function difference of 0.38 eV, have the least Drain-Induced Barrier Lowering (DIBL) of 12.88 mV/V. A better Sub-threshold Swing (SS) is observed for DMG-JLFinFET having ΦM1 < ΦM2. For devices with ΦM1 > ΦM2, SS can be improved by making a length of M1 (LM1) greater than 70% of the total gate length (Lg). © 2024 IETE.
Design of high throughput asynchronous FIR filter using gate level pipelined multipliers and adders
(John Wiley and Sons Ltd vgorayska@wiley.com Southern Gate Chichester, West Sussex PO19 8SQ, 2020) Girija Sravani, K.; Rao, R.
This work presents the design of an asynchronous digital finite impulse response (FIR) filter suitable for high-performance partial response maximum likelihood (PRML) read channel ICs. A high throughput, low latency FIR filter is the basic requirement for the equalization process in read channels. To achieve the enhancement in speed and reduction in latency of the FIR filter, its computational units are deeply pipelined using high-capacity hybrid (HC-hybrid) logic pipeline method. The designed FIR filter has been simulated using UMC-180 nm and UMC-65 nm technologies. Simulation results show that the asynchronous digital FIR filter can operate up to a throughput of 1.17 Giga items/s in 180 nm and 2.3 Giga items/s in 65 nm technology yet with the latency in the order of ns. © 2020 John Wiley & Sons, Ltd.
Design, analysis and testing of flexurally amplified piezoactuator based active vibration isolation system for micromilling
(Bangladesh University of Engineering and Technology, 2020) Divijesh, P.; Rao, M.; Rao, R.; Ahmed, R.M.; Sushith, K.
Vibration is considered to be one of the limiting factors which affects precise measurements and surface finish of various mechanical components. Active Vibration Isolation is one such effective method which reduces the unwanted vibrations in any mechanical systems in a wide range of frequencies. This paper presents the design, analysis and testing of an active vibration isolation system based on Flexurally Amplified Piezo actuators (FAP1 and FAP2). The proposed set up aims at obtaining 180° out of phase displacement signal to the generated displacement signal using FAPs thereby minimising vibrations at the isolation platform. The maximum displacements of FAP1 and FAP2 obtained for 0-150V sinusoidal peak to peak amplitude at 1Hz frequency was found to be 810?m and 780?m respectively. The experimental displacements obtained were compared with simulated displacements using Forward Bouc-Wen hysteresis model and found very well agreed with each other within 1% error. An attempt has been made to estimate the voltage required for obtaining any desired displacement of FAPs using Inverse Bouc-Wen model through Simulink. The experimental displacements for the corresponding estimated voltages were obtained for FAPs. Finally, the proposed set up was tested by actuating both FAP1 and FAP2 separately and simultaneously for 0-150V at 1Hz frequency and was found that the displacements obtained were 180° out of phase thereby minimizing vibrations at the isolation platform. © 2020 Zibeline International Publishing Sdn. Bhd.. All rights reserved.
Development of piezoactuator based rotary tool feeding system for micro-EDM
(Elsevier Ltd, 2022) Venugopal, T.R.; Rao, M.; Rao, R.; Sushith, K.
Micro Electrical Discharge Machining (micro-EDM) is widely employed for the fabrication of component parts used in Micro Electro Mechanical System (MEMS) devices and many other applications. Spark gap, being a critical process parameter in micro-EDM, must be maintained at optimum length for stable machining. To meet this critical requirement, the tool feeding system employed in micro-EDM must be capable of feeding the tool electrode adaptively to maintain the optimum spark gap. This paper proposes to develop a Flexurally Amplified Piezoactuator based rotary tool feeding system for micro-EDM. Hysteresis behavior of the piezoactuated tool feeding system is modeled using Maxwell's hysteresis model. Model based tool feed control experiments were conducted for different feed displacements ranging from 100 Î¼m to 600 Î¼m and spindle rotational speeds from 400 rpm to 1800 rpm. From the experimental results it is observed that the developed rotary tool feeding system performs with an error less than 1% for larger feed displacements at higher spindle speeds. Machining experiment with tool rotation enhanced blind hole depth by 29.21% compared to machining without tool rotation. [copyright information to be updated in production process]. Â© 2022 Elsevier Ltd. All rights reserved.
Displacement characteristics of a piezoactuator-based prototype microactuator with a hydraulic displacement amplification system
(2015) Muralidhara; Rao, R.
In this study, a new piezoactuator-based prototype microactuator is proposed with a hydraulic displacement amplification system. A piezoactuator is used to deflect a diaphragm which displaces a certain volume of hydraulic fluid into a smaller-diameter piston chamber, thereby amplifying the displacement at the other end of the piston. An electro-mechanical model is implemented to estimate the displacement of a multilayer piezoelectric actuator for the applied input voltage considering the hysteresis behavior. The displacement characteristics of the proposed microactuator are studied for triangular actuation voltage signal. Results of the experiments and simulation of the displacement behavior of the stacked piezoactuator and the amplified displacement of the prototype actuator were compared. Experimental results suggest that the mathematical model developed for the new piezoactuator-based prototype actuator is capable of estimating its displacement behavior accurately, within an error of 1.2%. 2015, The Korean Society of Mechanical Engineers and Springer-Verlag Berlin Heidelberg.
Displacement characteristics of a piezoactuator-based prototype microactuator with a hydraulic displacement amplification system
(Korean Society of Mechanical Engineers, 2015) Rao, M.; Rao, R.
In this study, a new piezoactuator-based prototype microactuator is proposed with a hydraulic displacement amplification system. A piezoactuator is used to deflect a diaphragm which displaces a certain volume of hydraulic fluid into a smaller-diameter piston chamber, thereby amplifying the displacement at the other end of the piston. An electro-mechanical model is implemented to estimate the displacement of a multilayer piezoelectric actuator for the applied input voltage considering the hysteresis behavior. The displacement characteristics of the proposed microactuator are studied for triangular actuation voltage signal. Results of the experiments and simulation of the displacement behavior of the stacked piezoactuator and the amplified displacement of the prototype actuator were compared. Experimental results suggest that the mathematical model developed for the new piezoactuator-based prototype actuator is capable of estimating its displacement behavior accurately, within an error of 1.2%. © 2015, The Korean Society of Mechanical Engineers and Springer-Verlag Berlin Heidelberg.
Experimental investigation on the suitability of flexible pressure sensor for wrist pulse measurement
(2019) Rao, M, S.; Rao, R.
Pulse examination at the radial artery of the wrist is a most apparent diagnosis technique. Wrist pulse carries rich information about the cardiovascular system of human body. An investigation is made here to suggest suitable flexible type of thin film pressure sensor to measure the wrist pulse as per Ayurvedic medicine system. Primary objective of this work is to suggest a sensor which exhibits optimum spatial features and SNR values. Force Sensing Resistor (FSR), piezoresistive and piezoelectric thin film sensors are considered under this study. Piezoelectric sensor shows good performance in the quality of the pulse with 22 dB SNR. Further experimentation is conducted to find out transmissivity, repeatability and susceptibility to motion artifact. Trasnsmissivities of 0.91, 0.68 and 0.64 are obtained for piezoelectric, piezoresistive and FSR sensors respectively. Piezoresistive and FSR show repeatability error of 8% and 7% while measuring pulse amplitude under standard force. Noise due to motion artifact for each type of sensors are recorded and compared with the standard Gaussian distribution function with the help of histogram. Collectively, piezoelectric sensor exhibits good spatial features, high transmissivity and comparatively low susceptibility to motion artifact. 2018, IUPESM and Springer-Verlag GmbH Germany, part of Springer Nature.