A Full-Swing, High-Speed, and High-Impedance Hybrid 1-Bit Full Adder

Abstract

In this paper, an attempt has been made to design a high-speed architecture for a 1-bit full adder. The proposed circuit uses a hybrid structure that combines CMOS logic and Transmission gate logic for design and implementation. Using both CMOS and Transmission gate logic in a design can provide the advantages of both the logic design. The SPICE simulations for the proposed full adder circuit have been performed with TSMC 180 nm CMOS Technology. The proposed full adder circuit has 23.63% less carry delay than the sum delay, which can be exploited for use in more complex systems like multi-bit adders where the carry path becomes the critical path. The speed of the proposed full adder is found to improve by 32.6% and 8.03% for sum and carry, respectively, with respect to CMOS implementation and by 1.62% and 21.02% with respect to some of the best-reported architectures in the literature. The proposed circuit has been found to have high input impedance and a low output impedance along with a full swing of voltages at the output. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.