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Title: 14.5 fJ/conversion-step 9-bit 100-kS/s nonbinary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS
Authors: Narasimaiah, J.D.
Bhat, M.S.
Issue Date: 2018
Citation: IET Circuits, Devices and Systems, 2018, Vol.12, 6, pp.671-680
Abstract: In this work, design technique and analysis of low-energy consumption successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. A dual capacitor array (CA) generates a digital-to-analogue reference voltage with increased accuracy. The CA supports multiple parallel operations to enhance conversion speed. Unit sized capacitors in CAs are few in number and present good capacitance density, thereby providing area efficiency and ease of routeing. A 9-bit SAR ADC using the proposed dual CA, implemented in a 90 nm CMOS process, has a small core area footprint of 0.00371 mm2. At a 1 V supply and 100 kS/s, the ADC achieves a signal-to-noise and distortion ratio of 53.55 dB and consumes 0.47 ?W, resulting in a figure-of-merit of 14.5 fJ/conversion step. The Institution of Engineering and Technology 2018.
URI: 10.1049/iet-cds.2018.5067
Appears in Collections:1. Journal Articles

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