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|Title:||Performance enhancement in high speed on-chip interconnect lines|
|Authors:||Soorya, Krishna, K.|
|Citation:||2010 5th International Conference on Industrial and Information Systems, ICIIS 2010, 2010, Vol., , pp.228-233|
|Abstract:||An interconnect line along with a series inductor can be used as a resonant network for transmitting high frequency data/clock in an integrated circuit. In this paper, the design of an active inductor circuit and its use in a global interconnect line to form a resonant network for reducing interconnect delay and area is described. An active inductor in place of on-chip passive inductor reduces interconnect latency by 38% and area by 300 times at an operating frequency of 2 GHz in 0.18 ?m technology. Monte Carlo simulations are carried out to find the range of interconnect delay variations and output voltage fluctuations due to process and mismatch variations in the active inductor circuit. �2010 IEEE.|
|Appears in Collections:||2. Conference Papers|
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