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|Title:||Energy efficient 1.8 V step down DC/DC converter in 0.18 ?m CMOS technology with optimized silicon area|
|Citation:||ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology, 2011, Vol.2, , pp.330-334|
|Abstract:||We present a power efficient DC to DC Converter to step down unregulated DC voltage source of 2.7-3.6 V to the regulated 1.8 V DC. The DC to DC Converter, constituted here, is designed for the load current range of 0 to 100 mA. It offers the output voltage ripple and the steady state error less than 1% of the nominal load voltage. The step down converter switches at the frequency of 5 MHz causing substential reduction in the size of the filter inductor and capacitor. This reduction is expoilted to achieve good transient response in case of sudden load change. The Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM) switching is used to stipulate approximately 88% of power effiecieny over almost entire range of the load current. This paper also gives mathematical foundation to determine optimum size for a power switch in order to balance out the swiching loss and the ON state loss of the switch under high load condition thereby it redeems the silicon real estate. � 2011 IEEE.|
|Appears in Collections:||2. Conference Papers|
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