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Title: A low-energy area-efficient dual channel SAR ADC using common capacitor array technique
Authors: Reddy, N.S.
Jagadish, D.N.
Bhat, M.S.
Issue Date: 2016
Citation: 2016 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2016 - Proceedings, 2016, Vol., , pp.148-152
Abstract: A novel low energy and area efficient Dual-Channel Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is presented. To achieve area efficiency, a common Capacitor Array (CA) technique is proposed wherein we use only N+1 CAs instead of 2N for N-channels in a differential architecture. In the present design we use three CAs instead of four for two channels. This reduction in CA count not only reduces the capacitance area but also the total energy required to charge and discharge the CAs. A 7-bit dual channel SAR ADC using the proposed technique is implemented in UMC 0.18?m CMOS technology. At a sampling rate of 4 MS/s and a supply voltage of 1.8 V, each channel consumes 43.85 ?W and exhibits a FOM of 101.14 fJ/conversion step. � 2016 IEEE.
Appears in Collections:2. Conference Papers

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