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Title: Triple reduced surface field drain extended MOS device design and its RF performance evaluation for sub-micron RF SoC platform
Authors: Somayaji, B.J.
Bhat, M.S.
Issue Date: 2017
Citation: Journal of Low Power Electronics, 2017, Vol.13, 4, pp.669-677
Abstract: This paper presents the design of RESURF based non-conventionalDrain ExtendedMOS (DEMOS) and its parametric analysis. The work investigates the impact of three primary parameters relating to p-implant, namely implant placement distance, implant doping and implant thickness, on device performance and premature avalanche breakdown. To avoid undesirable implant-drain punch-through, a boundary of limits is proposed near drain. Further, the implant parameters are optimized to maximize the ratio of Breakdown Voltage (BVt) to ON-resistance (RON). A breakdown voltage of 21 V at a low RON of 2.5 k? was achieved for a device gate length of 250 nm and gate oxide thickness of 5 nm. Using the optimized device design, the RF/Analog performance parameters are extracted and evaluated to enhance the suitability of the device for high voltage I/O applications in Sub-micron RF-SoC. Copyright � 2017 American Scientific Publishers All rights reserved Printed in the United States of America.
Appears in Collections:2. Conference Papers

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