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Title: Performance and Reliability Codesign for Superjunction Drain Extended MOS Devices
Authors: Somayaji, J.
Kumar, B.S.
Bhat, M.S.
Shrivastava, M.
Issue Date: 2017
Citation: IEEE Transactions on Electron Devices, 2017, Vol.64, 10, pp.4175-4183
Abstract: Conventionally, integrated drain-extended MOS (DeMOS) like high-voltage devices are designed while keeping only performance targets for a given application in mind. In this paper, for the first time, performance and reliability codesign approach using 3-D TCAD has been presented for various superjunction (SJ) type DeMOS devices. In this context, how to effectively utilize the SJ concept in a DeMOS device for System on Chip applications, which often has stringent switching and RF performance targets, is explored in detail in this paper. Moreover, design and reliability tradeoffs for switching and RF applications are discussed, while considering two unique sets, one with fixed breakdown voltage and other with fixed ON-resistance. Finally, hot carrier generation, safe operating area concerns, and electrostatic discharge physics are explored and compared using 3-D TCAD simulations. 1963-2012 IEEE.
Appears in Collections:1. Journal Articles

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