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Results 1-10 of 19 (Search time: 0.002 seconds).
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Issue Date
Title
Author(s)
Supervisor(s)
2019
High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs
Prabhu, P.B.M.
;
Parane, K.
;
Talawar, B.
-
2019
High-performance NoC simulation acceleration framework employing the xilinx DSP48E1 blocks
Prabhu, Prasad, B.M.
;
Parane, K.
;
Talawar, B.
-
2016
Analysis of ring topology for NoC architecture
Kamath, A.
;
Saxena, G.
;
Talawar, B.
-
2019
MMAS on GPU for Large TSP Instances
Yelmewad, P.
;
Kumar, A.
;
Talawar, B.
-
2019
Design of an adaptive and reliable network on chip router architecture using FPGA
Parane, K.
;
Prabhu, Prasad, B.M.
;
Talawar, B.
-
2018
Floorplan based performance evaluation of 3d variants of mesh and BFT networks-on-chip
Halavar, B.
;
Talawar, B.
-
2018
FPGA based NoC Simulation Acceleration Framework Supporting Adaptive Routing
Parane, K.
;
Prabhu, Prasad, B.M.
;
Talawar, B.
-
2018
Near Optimal Solution for Traveling Salesman Problem using GPU
Yelmewad, P.
;
Talawar, B.
-
2019
A Support Vector Regression-Based Approach to Predict the Performance of 2D 3D On-Chip Communication Architectures
Kumar, A.
;
Talawar, B.
-
2018
Accurate Power and Latency Analysis of a Through-Silicon Via(TSV)
Pasupulety, U.
;
Halavar, B.
;
Talawar, B.
-
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Author
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Parane, K.
5
Prabhu, Prasad, B.M.
4
Halavar, B.
4
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2
Pasupulety, U.
2
Yelmewad, P.
1
Kamath, A.
1
Prabhu, P.B.M.
1
Prasad, P.
1
Radhakrishnan, V.
.
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2018
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2019
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false