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Results 1-9 of 9 (Search time: 0.004 seconds).
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Issue Date
Title
Author(s)
Supervisor(s)
2010
Impedance matching for the reduction of via induced signal reflection in on-chip high speed interconnect lines
Krishna, K, S.
;
Bhat, M.S.
-
2012
Switched inverter comparator based 0.5 v low power 6 bit Flash ADC
Komar, R.
;
Bhat, M.S.
;
Laxminidhi, T.
-
2012
Zero delay clocking system in GHz frequency regime using CRLH metamaterial structure
Soorya, K.K.
;
Bhat, M.S.
-
2012
A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC
Shrivastava, P.
;
Bhat, K.G.
;
Laxminidhi, T.
;
Bhat, M.S.
-
2010
Estimation of interconnect metrics using state space approach
Soorya, Krishna, K.
;
Pramod, M.
;
Bhat, M.S.
-
2019
A Scheme for efficient and equitable use of public utilities through supervisory and distributed control
Shreenivasa, K.
;
Bhat, M.S.
;
Rekha, S.
-
2019
Library Characterization: Noise and Delay Modeling
Raj, R.
;
Bhat, M.S.
;
Rekha, S.
-
2011
Selective image smoothing and feature enhancement using modified shock filters
Bini, A.A.
;
Bhat, M.S.
-
2019
A Compact 10-bit Nonbinary Weighted Switched Capacitor Integrator Based SAR ADC Architecture
Bhat, K.G.
;
Laxminidhi, T.
;
Bhat, M.S.
-
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Shrivastava, P.
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Soorya, K.K.
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Soorya, Krishna, K.
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