Design and Mathematical Modeling of Dual Material Gate Junctionless Finfet

Abstract

Junctionless transistor (JLT) is a type of eld e ect transistor without any p-n junctions in its active region. Unlike conventional MOSFET, when JLT scales down in size, creating very small and shallow source and drain regions in a substrate containing dopants of opposing polarity is not needed. This simpli es the fabrication process to a great extent. In- corporating Dual Material Gate (DMG) architecture in JLT signi cantly enhances transistor performance in terms of reduced Short Channel Ef- fects (SCE), better threshold voltage engineering and enhanced control over channel electrostatics. Hence a detailed investigation of the elec- trical behaviour and SCE in Dual Material Gate Junctionless Fin Field E ect Transistors(DMG JLFinFETs) with di erent gate material combi- nations and various gate metal length ratios is conducted in this research work. Rigorous analysis on the DC and short channel performance of DMG JLFinFET with gate length as low as 10 nm is done using the de- vice simulator ATLAS provided by Silvaco, Inc. It is observed that by properly selecting gate materials and with suitable gate length ratios, the performance of DMG JLFinFET can be enhanced while keeping SCE at bay. In a DMG JLFinFET, it is the di erence in the work function of both gate materials that decides Drain Induced Barrier Lowering (DIBL) and Sub-threshold Swing (SS) and not their individual work functions. Based on these observations, design guidelines are provided to choose the gate materials in a DMG JLFinFET as per the requirements. Of all combi- nations of DMG pairs examined, least DIBL of 12.88 mV/V is obtained when ϕM1 − ϕM2 is 0.38 eV (Titanium-Aluminium and Nickel-Titanium gate pair). The degree of enhancement in the performance of DMG JLFin- FET by choosing suitable spacers with proper spacer lengths (LSP) is also examined. Best performance is observed in DMG JLFinFETs with HfO2 spacer having a length of 50% of source/drain extension length. As transistors are building blocks of Intergrated Circuits (ICs), developing robust and computationally e cient mathematical models is necessary to design complex ICs. DMG JLFinFETs showcase exemplary performance like negligible Drain Induced Barrier lowering (DIBL) and reasonably less Sub-threshold Swing (SS) alongside easier tuning of their threshold volt- age. Hence it is imperative to model their characteristics. In this work, initially, Fourier series-based analytical model for threshold voltage (Vth) and SS are developed for Single Material Gate JLFinFET (SMG JLFin- FET) on SOI substrate. These models take into account the location of the onset of current conduction in the channel. Therefore they are more accurate in predicting Vth and SS than the model available in the literature using the same approach. At channel length of 12 nm maximum deviation of threshold voltage calculated using the proposed model and numerical simulation is 1.46 V as against similar error of 3.19 V using the published model. SS model derived in this work gave a maximum error of 153.27 mV/dec whereas with the published model, the highest error was 382.95 mV/dec. It is seen that DMG JLFinFET outperforms SMG counterpart in terms of current characteristics as well as SCE. However, there is no literature available that discusses the mathematical modeling of various parameters of DMG JLFinFET. Hence, Fourier series-based channel po- tential and Vth models for DMG JLFinFET are developed and validated using TCAD simulations.