Technology driven high-level synthesis

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dc.contributor.authorJoseph, M.
dc.contributor.authorBhat Narasimha, N.B.
dc.contributor.authorChandra Sekaran, K.C.
dc.date.accessioned2026-02-06T06:41:04Z
dc.date.issued2007
dc.description.abstractTechnology driven High-Level Synthesis make the present High-Level Synthesis knowledgeable of the target Field Programmable Gate Array. All the functions of High-Level Synthesis become aware of target technology since parsing. It makes right inference of hardware, by attaching target technology specific attributes to the parse tree. This right inference will guide to generate optimized hardware. © 2007 IEEE.
dc.identifier.citationProceedings of the 15th International Conference on Advanced Computing and Communications, ADCOM 2007, 2007, Vol., , p. 485-490
dc.identifier.urihttps://doi.org/10.1109/adcom.2007.39
dc.identifier.urihttps://idr.nitk.ac.in/handle/123456789/33336
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.subjectAttribute grammars
dc.subjectFPGA
dc.subjectHigh-level synthesis
dc.subjectOptimization
dc.subjectTarget technology
dc.titleTechnology driven high-level synthesis

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