Technology driven high-level synthesis
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Date
2007
Journal Title
Journal ISSN
Volume Title
Publisher
Institute of Electrical and Electronics Engineers Inc.
Abstract
Technology driven High-Level Synthesis make the present High-Level Synthesis knowledgeable of the target Field Programmable Gate Array. All the functions of High-Level Synthesis become aware of target technology since parsing. It makes right inference of hardware, by attaching target technology specific attributes to the parse tree. This right inference will guide to generate optimized hardware. © 2007 IEEE.
Description
Keywords
Attribute grammars, FPGA, High-level synthesis, Optimization, Target technology
Citation
Proceedings of the 15th International Conference on Advanced Computing and Communications, ADCOM 2007, 2007, Vol., , p. 485-490