FPGA Based Physical Unclonable Function (PUF)-A Hardware Security Macro for securing Smart Meter Systems in IoT Environment

Abstract

Internet of Things (IoT) has transformed the engineering approach towards solving a problem. The key components of an IoT system are smart devices, sensors, gateway, cloud and user interface. The entire process of layered communication among these components of IoT is transparent and hence the intercommunication presents a potential vulnerability to unauthorized access of such an environment. Consequently, it is imperative not only to ensure secure communication channels for data transactions, but also to protect the physical layer, safeguarding the devices against intrusions. Hardware security, particularly device identification, conventionally relies on cryptographic hardware, such as the Secure Hash Algorithm (SHA) or public/private key encryption algorithms. A formalization of this concept has evolved from physical one-way functions to Physically Unclonable Functions (PUFs). PUFs produce a response for a given challenge by performing a functional operation. The function is built based on physical manufacturing variations of the device to generate a unique secret identification code and is measured by its challenge response pair (CRP). Although Application-Specific Integrated Circuit (ASIC) based PUFs exist with controlled process variations, the present research proposes the implementation of PUFs on field programmable gate arrays (FPGAs) because of their reconfigurable architecture, which facilitates the creation of a dynamic hardware for an optimal balance between time to market and product quality. Configurable Ring Oscillator (CRO) based PUF circuits have proven effective in formulating strong PUF designs by incorporating non-linearity within the model and utilizing configurable inputs. It is optimized with space and resources available on FPGA devices. The present thesis constitutes the following key elements: • Designing the PUF. • Analyzing the PUF for steady responses. • Proposing a unique methodology for combating the environmental

noise factors, such as temperature and timing variations (static and dynamic), affecting the PUF response. • Validating the proposed methodology on: – FPGAs with only programmable logic on the FPGA fabric (Spartan- 3 series devices), necessitating an external processor for processing the response in generating the signature. – FPGAs possessing both Programming logic (PL) and Processor system (PS) within the FPGA fabric (Artix 7 series devices), allowing the use of PS and PL based architectures to process the PUF response through the PS on the chip. • Proposing a Multiplexer based PUF with an architectural enhancement to the existing PUF to make it stronger. The aforementioned methodology for extracting the responses is implemented on the proposed structure. The strength of new proposed PUF is analyzed with its performance metrics and efficiency with respect to hardware. • Evaluating the design efficiency of the proposed PUF for resisting the attacks by modeling an attack with machine learning based logistic regression algorithm. Results showed a significant resistance to attacks in comparison with conventional models of FPGA based PUFs. The design is validated on the aforementioned hardware and applied to a connected system model of PUF based authentication in an IoT environment, specifically for a smart meter system.