A high speed complementary pulse compressor and its implementation of FPGA

Abstract

This paper proposes a novel high speed radar pulse compressor implementation for complementary sequences. The high speed implementation is accomplished by incorporating the retiming technique to reduce the critical path of the circuit. In addition, unfolding the retimed pulse compressor further increases the speed by parallel operation. This concept is implemented on field programmable gate array (FPGA) and the experimental results demonstrate that, three-retimed-unfolded circuit (J = 3) is 2.78 times faster than the original circuit. © 2017 IEEE.