Modelling and analysis of lower metal on-chip interconnects using physical fabrication parameters

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dc.contributor.authorKulkarni, A.
dc.contributor.authorIteesh, V.A.
dc.contributor.authorSahith, S.R.
dc.date.accessioned2026-02-06T06:37:14Z
dc.date.issued2019
dc.description.abstractThis paper looks into the modelling and analysis of on-chip interconnects in the lower metal region of an Integrated Circuit (IC). A proposed π-interconnect model is quantitatively modelled and analysed and the delay time, td is used as a metric to measure performance change from ideal circuit simulations for varying interconnect lengths using a driver-load inverter pair. The π-model delay time performance is also compared with that of a layout of an driver-load inverter pair circuit and a 3-stage ring-oscillator circuit. The layout is generated using MOSIS SCMOS technology using ON Semiconductor C5 600nm device model with VDD = 5V. All modelling and analysis is done using open-source EDA tools and technology. © 2019 IEEE.
dc.identifier.citationProceedings - 2019 IEEE International Symposium on Smart Electronic Systems, iSES 2019, 2019, Vol., , p. 350-354
dc.identifier.urihttps://doi.org/10.1109/iSES47678.2019.00087
dc.identifier.urihttps://idr.nitk.ac.in/handle/123456789/30940
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.subjectDelay Time Analysis
dc.subjectInterconnect Modelling
dc.subjectOn chip Interconnect
dc.subjectOpen Source EDA
dc.titleModelling and analysis of lower metal on-chip interconnects using physical fabrication parameters

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