Modelling and analysis of lower metal on-chip interconnects using physical fabrication parameters

Abstract

This paper looks into the modelling and analysis of on-chip interconnects in the lower metal region of an Integrated Circuit (IC). A proposed π-interconnect model is quantitatively modelled and analysed and the delay time, td is used as a metric to measure performance change from ideal circuit simulations for varying interconnect lengths using a driver-load inverter pair. The π-model delay time performance is also compared with that of a layout of an driver-load inverter pair circuit and a 3-stage ring-oscillator circuit. The layout is generated using MOSIS SCMOS technology using ON Semiconductor C5 600nm device model with VDD = 5V. All modelling and analysis is done using open-source EDA tools and technology. © 2019 IEEE.