Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications

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dc.contributor.authorSomayaji, B.J.
dc.contributor.authorBhat, M.S.
dc.date.accessioned2026-02-06T06:38:37Z
dc.date.issued2017
dc.description.abstractThis paper presents the design of RESURF based non-conventional LDMOS and its parametric analysis. The work investigates the impact of three primary parameters relating to p-implant, namely implant placement distance, implant doping and implant thickness, on device performance and premature avalanche breakdown. To avoid undesirable implant-drain punch-through, a boundary of limits is proposed near drain. Further, the implant parameters are optimized to maximize the ratio of Breakdown Voltage Vs On-resistance R<inf>on</inf> to enhance the suitability of the device for High Voltage I/O applications in Sub-micron RF-SoC. A breakdown voltage of 21V at a very low R<inf>on</inf> of 2.5kΩ was achieved for a device gate length of 250nm and gate oxide thickness of 5nm. © 2016 IEEE.
dc.identifier.citationProceedings - 2016 6th International Symposium on Embedded Computing and System Design, ISED 2016, 2017, Vol., , p. 72-76
dc.identifier.urihttps://doi.org/10.1109/ISED.2016.7977057
dc.identifier.urihttps://idr.nitk.ac.in/handle/123456789/31788
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.subjectBreakdown
dc.subjectDepletion
dc.subjectElectric-field
dc.subjectON-resistance
dc.subjectP-implant
dc.subjectPunch-through
dc.titleAnalysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications

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