Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications
No Thumbnail Available
Date
2017
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
Institute of Electrical and Electronics Engineers Inc.
Abstract
This paper presents the design of RESURF based non-conventional LDMOS and its parametric analysis. The work investigates the impact of three primary parameters relating to p-implant, namely implant placement distance, implant doping and implant thickness, on device performance and premature avalanche breakdown. To avoid undesirable implant-drain punch-through, a boundary of limits is proposed near drain. Further, the implant parameters are optimized to maximize the ratio of Breakdown Voltage Vs On-resistance R<inf>on</inf> to enhance the suitability of the device for High Voltage I/O applications in Sub-micron RF-SoC. A breakdown voltage of 21V at a very low R<inf>on</inf> of 2.5kΩ was achieved for a device gate length of 250nm and gate oxide thickness of 5nm. © 2016 IEEE.
Description
Keywords
Breakdown, Depletion, Electric-field, ON-resistance, P-implant, Punch-through
Citation
Proceedings - 2016 6th International Symposium on Embedded Computing and System Design, ISED 2016, 2017, Vol., , p. 72-76