Faculty Publications

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    Recent advancements in switched capacitor-based multilevel inverters
    (River Publishers, 2025) Kumar, D.; Raushan, R.; Kumari, D.; Bhushan, R.
    This chapter comprehensively reviews recent advances in switched capacitorbased multilevel inverters (SCMLIs) within the realm of power electronics. It outlines the fundamental principles of multilevel inverters, underscoring the role of switched capacitors in achieving higher voltage levels and refined waveform quality. The chapter critically examines the challenges in switched capacitor-based multilevel inverter designs, emphasizing recent research on circuit topologies and modulation strategies, including aspects like voltage balancing. Moreover, it discusses the integration of SCMLIs in electric vehicles and renewable energy systems and highlights their potential to enhance efficiency, improve power quality, and seamlessly integrate with modern power grids. The chapter succinctly captures the forefront of SCMLI technology, offering insights into its transformative impact on ongoing innovation to address evolving challenges in inverter topologies. © 2025 River Publishers. All rights reserved.
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    A Single Stage Switched-Capacitor Hexad Boost Multilevel Inverter Featuring Boost Ability
    (Institute of Electrical and Electronics Engineers Inc., 2020) Shiva Naik, B.S.; Yellasiri, Y.; Venkataramanaiah, J.
    Nowadays, curtailment in the number of dc sources, circuit component count along with the boosting gain property of the output voltage are considered as the essential topological features for the new multilevel inverter (MLI) structures. Considering the above, a novel 13-level single-stage switched-capacitor hexad boost (S3 CHB) inverter featuring boosting gain and self-balancing ability is proposed in this paper. Each phase of the proposed \mathrm{S}^{3} CHB-MLI is designed with only 14 semiconductor switches and three electrolytic capacitors. Here, the capacitors' voltages are balanced automatically by utilizing the series-parallel technique effectively. An absence of H-bridge at the back-end makes the circuit to extend for higher levels. Capacitors' voltage ripple are analyzed in detail. Further, a cost comparison is conducted among the state-of-art MLIs to highlight the superiority of the proposed configuration. Finally, the effectiveness of the proposed \mathrm{S}^{3} CHB circuit is experimentally demonstrated. Results at different load conditions are captured to prove the inductive load capability. © 2020 IEEE.
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    11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energyefficient successive approximation register ADC in 90 nm complementary metal-oxide- semiconductor
    (Institution of Engineering and Technology journals@theiet.org, 2018) Narasimaiah, J.D.; Laxminidhi, T.; Bhat, M.S.
    In this study, a design technique for low-energy consumption and area-efficient successive approximation register analogue-to-digital converter (ADC) is presented. Digital-to-analogue conversion equivalent voltage is acquired utilising passive sharing of charge between two unit capacitors and integration of the shared charge onto an input sample-and-hold capacitor, via a switched capacitor integrator circuit. The architecture is less parasitic sensitive and low noise, yielding an area and energyefficient ADC. To demonstrate the efficacy of the proposed technique, a ±350 mV 8 bit 0.78 MS/s ADC is designed in a 90 nm complementary metal-oxide-semiconductor process. The ADC core has a small area footprint of 0.00145 mm2 and has a figure-of-merit of 11.39 fJ/conv-step. © 2018, The Institution of Engineering and Technology.
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    A Switched-Capacitor-Based Multilevel Inverter Topology with Reduced Components
    (Institute of Electrical and Electronics Engineers Inc., 2018) Sandeep, N.; Yaragatti, U.R.
    This letter presents an improved sensorless nine-level inverter topology with reduced number of components. It is formed by cascading a three-level T-Type neutral clamped point inverter with a floating capacitor (FC) fed two-level converter unit. Additionally, two line-frequency switches are appended across the dc-link. A simple logic-form equations-based pulse width modulator is designed which is in-charge of maintaining the FC voltage at its reference value without any aid of voltage and current sensor. Thus, the complexity in control of the proposed topology is very minimal. The working principle of the proposed inverter and formulation of logic-form equations is deliberated in detail. Furthermore, experimental results obtained from the developed prototype are presented to validate feasibility and operability of the proposed topology. Finally, a comprehensive comparison with some of the recently reported inverter topologies proving the merits of the proposed topology is included. © 1986-2012 IEEE.
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    Switched-Capacitor-Based Quadruple-Boost Nine-Level Inverter
    (Institute of Electrical and Electronics Engineers Inc., 2019) Sandeep, N.; Jagabar Sathik, J.S.; Yaragatti, U.R.; Krishnasamy, K.
    This letter describes a novel nine-level inverter based on switched capacitors (SCs) with quadruple-boost ability requiring reduced components. The structure of the proposed topology relies on the series/parallel connection of SCs. It consists of 12 switches and two SCs. As opposed to similar SC-based inverters, the proposed topology does not employ a back-end H-bridge and the voltage stress of all the switches does not exceed twice the input dc voltage. A simple logic-gate-based pulsewidth-modulation scheme is developed for gating the switches of the proposed topology. A comprehensive comparison against the state-of-the-art topologies in terms of the required number of components is performed to attest the outperforming merits of the proposed topology. Finally, various experimental results are presented to validate the feasibility and operability of the proposed topology. © 1986-2012 IEEE.
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    A 1.8 V 8.62 µW Inverter-based Gain-boosted OTA with 109.3 dB dc Gain for SC Circuits
    (Taylor and Francis Ltd, 2019) Kaliyath, Y.; Laxminidhi, T.
    This paper presents a low-power inverter-based gain-boosted operational transconductance amplifier (OTA) for switched capacitor (SC) circuits operating at higher supply voltage (>1 V). The proposed OTA is implemented using UMC 180 nm CMOS technology with a supply voltage of 1.8 V and it offers a high dc gain with a unity gain bandwidth (UGB) suitable for audio applications. All the transistors of the proposed OTA are operated in sub-threshold region to minimize the power consumption. Gain-boosting technique is employed to achieve a higher dc gain. The post-layout simulations demonstrate the robust performance of the proposed OTA, which delivers a high dc gain of 109.3 dB and a UGB of 5.29 MHz at 81° phase margin (PM) with a capacitive load of 2.5 pF for a typical process corner at room temperature (27°C). The proposed OTA draws a quiescent current ((Formula presented.)) of 4.79 µA, resulting in a power consumption of 8.62 µW. © 2019, © 2019 IETE.
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    A Single DC Source Nine-Level Switched-Capacitor Boost Inverter Topology with Reduced Switch Count
    (Institute of Electrical and Electronics Engineers Inc., 2020) Siddique, M.D.; Alamri, B.; Salem, F.A.; Orabi, M.; Mekhilef, S.; Shah, N.M.; Sandeep, N.; Jagabar Sathik, J.S.; Iqbal, A.; Ahmed, M.; Ghoneim, S.S.M.; Al-Harthi, M.M.
    This paper presents a new boost inverter topology with nine level output voltage waveform using a single dc source and two switched capacitors. The capacitor voltages are self-balancing and thus is devoid of any sensors and auxiliary circuitry. The output voltage is twice higher than the input voltage, which eliminates the need for an input dc boost converter especially when the inverter is powered from a renewable source. The merits of the proposed topology in terms of the number of devices and cost are highlighted by comparing the recent and conventional inverter topologies. In addition to this, the total voltage stress of the proposed topology is lower and have a maximum efficiency of 98.25%. The operation and dynamic performance of the proposed topology have been simulated using PLECS software and are validated using an experimental setup considering a different dynamic operation. © 2013 IEEE.
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    Experimental verification of a hybrid multilevel inverter with voltage-boosting ability
    (John Wiley and Sons Ltd vgorayska@wiley.com Southern Gate Chichester, West Sussex PO19 8SQ, 2020) Shiva Naik, B.; Yellasiri, Y.; Venkataramanaiah, J.
    A new nine-level natural-balanced boost hybrid multilevel inverter (BH-MLI) is proposed in this paper. Each phase of the proposed BH-MLI is designed with only 11 semiconductor switches and two electrolytic capacitors. Here, the capacitor voltages are balanced by utilizing the series-parallel and natural balancing techniques effectively. Furthermore, the proposed circuit eradicates the multiple DC sources by introducing a single DC link for single- and three-phase applications. The proposed topology can be easily extendible to obtain higher level output voltage waveform due to its modular-switched capacitor cells (SCCs). Besides, the higher voltage level generation does not pose high-voltage stress on any of the topology components, as the blocking voltage of all devices within the source voltage magnitude. Further, a quantitative comparison is conducted among the state-of-art switched-capacitor multilevel inverter (SC-MLIs) to highlight the superiority of the proposed configuration. Finally, the performance of the proposed BH-MLI is experimentally validated with phase disposition-pulse width modulation (PD-PWM) and round control method at different modulation indices, load conditions. © 2020 John Wiley & Sons, Ltd.
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    Seven-level boosting active neutral point clamped inverter using cross-connected switched capacitor cells
    (Institution of Engineering and Technology jbristow@theiet.org, 2020) Jagabar Sathik, M.J.; Sandeep, N.; Almakhles, D.; Bhatnagar, K.; Yang, Y.; Blaabjerg, F.
    In this study, an active neutral point clamped-type boosting switched-capacitor multilevel inverter (SCMLI) with selfvoltage balancing capability is proposed. In the proposed topology, a novel switched capacitor cell is used, which has eightswitches and two diodes. The presented topology has reduced power component count with self-boosting and balancingabilities. The distinctive features of the proposed topology are highlighted and benchmarked against other recent 7L-SCMLItopologies. To validate the feasibility of the proposed topology, experimental tests are performed on a 1 kW prototype hardwaresetup. © 2020 The Institution of Engineering and Technology.
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    A novel nine-level boost inverter with a low component count for electric vehicle applications
    (John Wiley and Sons Ltd, 2021) Shiva Naik, B.S.; Yellasiri, Y.; Aditya, K.; Nageswar Rao, B.N.
    In electric vehicles (EVs), considerable battery cells are cascaded in series for motor driving to improve the output voltage. The series combination of battery cells causes challenges like isolation of faulty cells, voltage unbalance, and slow charge equalization. Therefore, state-of-charge (SOC) and voltage equalization circuits are often used in industries to protect the battery cells. A nine-level inverter circuit with a double voltage boost is proposed to reduce the above issues based on the switch-capacitor (SC) principle. Unique features like self-balancing, voltage boosting are attained, which cannot be achieved through traditional inverters. The proposed topology can operate at a wide range of modulation indices ((Formula presented.)) to produce different voltage levels. The absence of a back-end H-bridge in the proposed circuit offers low voltage stress across the semiconductors. The operating principle, capacitor sizing, and modulation approach are presented. Further, experimental tests are conducted at different loading conditions to verify the performance of the proposed circuit. © 2021 John Wiley & Sons Ltd.