Faculty Publications
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Publications by NITK Faculty
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Item High-Performance Graphene FET Integrated Front-End Amplifier Using Pseudo-resistor Technique for Neuro-prosthetic Diagnosis(SpringerOpen, 2022) Naik, J.D.; Gorre, P.; Akuri, N.G.; Kumar, S.; Al-Shidaifat, A.D.; Song, H.A complex analysis of spike monitoring in neuro-prosthetic diagnosis demands a high-speed sub-nanoscale transistors with an advanced device technologies. This work reports the high performance of Graphene field-effect transistor (GFET) based front-end amplifier (FEA) design for the neuro-prosthetic application. The 9 nm Graphene FET device is optimized by characterization of transconductance and drain current towards high sensitivity and small factor. The proposed GFET-based FEA with pseudo-resistor technique demonstrates very high-input impedance in Tera-ohms that nullify the input leakage current. Here, gain-bandwidth product and noise optimization of GFET FEA enhances the overall gain with negligible noise. The proposed design operates at low voltage, further reduces the power consumption, and achieves less chip area in sub-nano size so it could be more suitable for implantable devices. The GFET-based FEA architecture achieves an action potential spike of 1.4 µV while the local field potentials spike of 1.8 mV. The proposed architecture is implemented in Advanced Design System using the design kit of the GFET process. Power consumption of 3.14 µW is observed with a supply voltage of 0.9 V. The simulated and experimental results of the proposed design achieve an input impedance of 2 TΩ with excellent noise performance over a wideband of 13.85 MHz. The proposed work demonstrates better neural activity sensing when compared to the state-of-the-artwork, which could be highly beneficial for future neuroscientists. © 2022, The Korean BioChip Society.Item Performance assessment of pocket tunnel FET and accumulation mode FET for detection of streptavidin protein(Institute of Physics, 2023) Jadhav, A.; Yadav, S.; Pandey, S.K.; Garg, V.; Dwivedi, P.In this paper, Dielectrically Modulated (DM) pocket Tunnel Field Effect Transistor (TFET) and Accumulation Mode Field Effect Transistor (AMFET) biosensors are examined for the Sensitivity estimation of different thicknesses of biotarget (Streptavidin)/bioreceptor (Biotin)/silica binding protein (SBP or APTES) biomolecules with a fully filled and partially filled cavity. The sensitivity parameter is based on realistic process detection and is calculated as the ratio of biotarget to bioreceptor drain current for neutral and charged biomolecules. The effect on the sensitivity for a filled cavity is observed for: a) varying the thickness of streptavidin and Biotin for fixed SBP (APTES) thickness, b) varying the thickness of streptavidin and APTES for fixed biotin thickness, for both Pocket TFET and AMFET. The maximum sensitivity is observed in 4 nm thick streptavidin for the front gate voltage V fg: −3.8 V and V fg: −1.6 V for pocket TFET and AMFET, respectively. © 2023 IOP Publishing Ltd.Item Design of Dual-Material Gate Junctionless FinFET based on the Properties of Materials Forming Gate Electrode(Taylor and Francis Ltd., 2024) Mathew, S.; Bhat, K.N.; Nithin; Rao, R.This work elaborately investigates the electrical behaviour and short channel performance of Dual-Material Gate Junctionless Fin Field Effect Transistors (DMG-JLFinFETs) with multiple-gate metal pairs and varying gate metal length ratios. Rigorous analysis on the nature of DMG-JLFinFET with gate length as low as 10 nm is done using a device simulator by Silvaco, Inc. The gate material closer to the source, namely M1, has a dominating influence on the threshold voltage (Vth) and tunnelling current (Itunn) than the gate material closer to the drain (named M2) in a DMG-JLFinFET. Itunn is lower when the work function of M1 (ΦM1) is greater than the work function of M2 (ΦM2). The relative change in threshold voltage is minimum for Platinum–Gold (PtAu)-DMG-JLFinFET (0.68%). Titanium–Aluminium (TiAl) and Nickel–Titanium (NiTi) gate material pairs, having the same work function difference of 0.38 eV, have the least Drain-Induced Barrier Lowering (DIBL) of 12.88 mV/V. A better Sub-threshold Swing (SS) is observed for DMG-JLFinFET having ΦM1 < ΦM2. For devices with ΦM1 > ΦM2, SS can be improved by making a length of M1 (LM1) greater than 70% of the total gate length (Lg). © 2024 IETE.Item Performance Enhancement of Dual Material Gate Junctionless FinFETs using Dielectric Spacer(Taylor and Francis Ltd., 2024) Mathew, S.; Bhat, K.N.; Nithin; Rao, R.In this work, a detailed investigation is done on the effectiveness of various spacer materials having different spacer lengths (LSP), in improving the performance of Dual-Material Gate-Junctionless FinFET (DMG-JLFinFET). Various performance metrics, such as Drain Induced Barrier Lowering (DIBL), Sub-threshold Swing (SS), ON current (ION), OFF current (IOFF), ratio of ION to IOFF (ION/IOFF), and tunneling current (Itunn), are closely monitored at gate lengths (Lg) down to 10 nm. DIBL degradation of 3.46 mV/V and SS degradation of 4.97 mV/dec are observed when Lg scales down from 30 nm to 10 nm. Except for the case of Itunn, other performance metrics improve with an increase in dielectric constant and length of spacer materials. The optimum performance of DMG-JLFinFET with a channel length of 10 nm is obtained when LSP is 5 nm. Enhancement in analog performance metrics is observed when high κ materials are used as spacers. Transconductance Generation Factor (TGF) improves from 35.86 V−1 to 47.4 V−1 and intrinsic gain increases from 6.93 dB to 11.98 dB when high κ dielectric materials like TiO2 are incorporated as spacers in a DMG-JLFinFET. © 2024 IETE.