Performance Enhancement of Dual Material Gate Junctionless FinFETs using Dielectric Spacer

Abstract

In this work, a detailed investigation is done on the effectiveness of various spacer materials having different spacer lengths (L<inf>SP</inf>), in improving the performance of Dual-Material Gate-Junctionless FinFET (DMG-JLFinFET). Various performance metrics, such as Drain Induced Barrier Lowering (DIBL), Sub-threshold Swing (SS), ON current (I<inf>ON</inf>), OFF current (I<inf>OFF</inf>), ratio of I<inf>ON</inf> to I<inf>OFF</inf> (I<inf>ON</inf>/I<inf>OFF</inf>), and tunneling current (I<inf>tunn</inf>), are closely monitored at gate lengths (L<inf>g</inf>) down to 10 nm. DIBL degradation of 3.46 mV/V and SS degradation of 4.97 mV/dec are observed when L<inf>g</inf> scales down from 30 nm to 10 nm. Except for the case of I<inf>tunn</inf>, other performance metrics improve with an increase in dielectric constant and length of spacer materials. The optimum performance of DMG-JLFinFET with a channel length of 10 nm is obtained when L<inf>SP</inf> is 5 nm. Enhancement in analog performance metrics is observed when high κ materials are used as spacers. Transconductance Generation Factor (TGF) improves from 35.86 V−1 to 47.4 V−1 and intrinsic gain increases from 6.93 dB to 11.98 dB when high κ dielectric materials like TiO<inf>2</inf> are incorporated as spacers in a DMG-JLFinFET. © 2024 IETE.